The WAVE320 is a dual core H.264/AVC codec IP that is capable of up to 4Kx2K@30fps realtime video encoding or decoding for H.264/AVC stream. This core is the first member of WAVE platform based on an unique scalable multi-core architecture, which achieves exceptional performance while maintaining a very low clock frequency (4Kx2K 30fps at 266MHz).
In addition to support 4Kx2K ultra high-definition resolution, the WAVE320 also enables enhancing vewing experiences including fast-action sports and movies with 1080p video at 120frames per second, and multi-channel full HD browsing.(4 channel 1080p 30 video)
The WAVE320 video codec IP core is optimized for next generation devices including ultra high-definition televisions(UDTVs), set-top boxes(STBs), camcorders, DSCs, DSLRs, and other applications with support super high resolution. When paired with one of Chips&Media's CODA or BODA cores, the core can decode or encode multiple streams in different video standards to satisfy a wide range of applications.
Features
- Supported standards for Decoder
- ISO/IEC 14496-10 AVC(H.264) BP/MP/HP@L5.1
- Supported standards for Encoder
- ISO/IEC 14496-10 AVC(H.264) BP/MP/HP@L5.1
- Performancce
- Single stream decode up to 4Kx2K@30fps at 266MHz core clock frequency
- Single stream encode up to 4Kx2K@30fps at 266MHz core clock frequency
- Encoding Tools
- Fully compatible with with ISO/IEC 14496-10 AVC(H.264) specification in BP, MP and HP
- Supports MVC Stereo High Profile(ISO/IEC 14496-10/5)
- Supports up to 4096x2304 pixel resolution(4Kx2K)
- H.264/AVC intra-prediction
- CABAC/CAVLC for H.264/AVC
- In-loop deblocking filter for both H.264
- Flexible Bit-rate control
- Linear or tiled frame buffer
- Sub frame sync. for real-time applications
- Built-in pre processing unit
- Decoding Tools
- Fully compatible with with ISO/IEC 14496-10 AVC(H.264) specification in BP, MP and HP
- Supports MVC Stereo High Profile(ISO/IEC 14496-10/5)
- Supports up to 4096x2304 pixel resolution(4Kx2K)
- All variable block size supported
- Supports CABAD/CAVLD entropy decoding
- H.264/AVC intra-prediction
- In-loop deblocking filter
- Linear or tiled frame buffer
- Built-in post processing unit
- Interface
- AMBA 32-bit APB interface for Host CPU
- AMBA 64-bit AXI interface for the external memory
Benefits
- Provides high performance for decoding or encoding up to resolution of 4K30p
- Supports high frame-rate video for capturing fast-action sports with 1080p video at 120fps or 720p 240fps
- Delivers high quality encoding capability for video communication or real-time transcoding
- Memory challenge scheme including Tiled buffer map and 2D smart Cache
- Ultra-low power hardware architecture using multi-level clock gating
- Low host CPU resources under 1MIPS
- Proven performance with system level design that minimizes risk and time-to market
Deliverables
- Fully verified synthesizable RTL source code
- RTL test bench
- S/W User Guide
- Datasheet/Integration Guide
- Verification Guide
- Evaluation platform
Block Diagram of the Dual core H.264 supporting up to 4K Ultra HD video resolution
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