The CMS0014 has been designed from the ground-up for high-speed and gate-efficient implementation on FPGA and ASIC platforms and offers "near Shannon limit" performance when combined with an advanced LDPC decoder solution such as TurboConcept's TC4000.
The demodulator provides an adaptable starting point for receiver sub-systems to be used in the next-generation of digital TV set-top-boxes, VSAT terminals and related test and monitoring equipment.
- Support for CCM, VCM and ACM modes.
- Sync acquisition at -2dB C/N.
- Wide carrier acquisition range.
- Programmable symbol rate recovery
- few kSymb/s to >45 MSymb/s.
- Real IF, zero-IF or near-zero-IF.
- Variable ADC sampling frequency.
- Frame-by-frame (A)PSK selection.
- QPSK, 8PSK, 16APSK, 32APSK.
- Short (16kb) and normal (64kb) frames
- Frames with/without intra-frame Pilots.
- Standards compliance
- Single external clock source.
- Single external analogue AGC loop.
- All-digital timing and carrier recovery.
- Digital channel filtering.
- Optimised for ASIC, Xilinx and Altera.
- Verified with the TC4000 LDPC decoder.
- Evaluation boards available.
- Group-delay equalisation.
- Source-code, bitstream and/or netlist-level licence for FPGA or ASIC.
- Cycle/bit accurate simulation model (Matlab/C++).