eDP 1.5a RX PHY Samsung 14nm
This core IP commonly used for connecting a timing controller (TCON) to a host processor.
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Block Diagram of the eDP 1.5a RX PHY Samsung 14nm
Display IP
- VESA DSC (Display Stream Compression) 1.2b Video Encoder
- VESA DSC (Display Stream Compression) 1.2b Video Decoder
- Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC
- VDC-M (VESA Display Compression-M) Encoder
- VDC-M (VESA Display Compression-M) Decoder
- Display Stream Compression (DSC 1.2) Decoder