The USB 2.0 xPHY IP provides designers with a complete USB 2.0 OTG Physical Layer (PHY) IP solution, designed for low power mobile and consumer applications such as mobile internet devices, handheld game machines, feature rich smart phones, digital cameras and portable audio/video players. The USB 2.0 xPHY IP delivers approximately half the power and die area, compared to other solutions, for longer battery life and lower silicon cost. Designed for high yield, the IP implements architectural features make it less sensitive to variations in foundry process, device models, package and board parasitics. The USB2.0 xPHY integrates high speed and mixed-signal circuits to support High-Speed data transmission at 480Mbps and is backward compatible to Full-Speed (12Mbps) and Low-Speed (1.5Mbps) data rates. Electro Static Discharge (ESD) protection is included to give full support for host functionality, as well as a clock generation block with a PLL unit that ensures accurate Hi-Speed data transmission. When combined with Hi-Speed or On-The-Go (OTG) digital USB controllers, this IP delivers a complete, low power and small die-area on-chip physical transceiver solution for Hi-Speed and OTG enabled system-on-chip (SoC) designs.
Features
- Complete mixed-signal physical layer for single-chip USB 2.0 OTG and non-OTG applications
- Low power: <100mW (during HS packet transmission)*
- Small area: < 1mm2*
- High Yield – Architecture designed to improve key operating margins by having less sensitivity to variations due to foundry process, chip and board parasitics, and process device model variations
- Low pin count
- USB 2.0 Transceiver Macrocell Interface (UTMI+ Level 3) specifcation
- Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps) operation is compliant to the USB OTG Supplement
- Supports all OTG features, including Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
- On-chip PLL reduces clock noise and eliminates externalclock generator requirement
- Designed for minimal power dissipation for low-power and bus-powered devices
- Suspend, Resume, and Remote Wakeup mode support
Benefits
- Integrates high-speed, mixed-signal and custom CMOS circuitry designed to the UTMI+ Level 3 Specifcation
- Supports the USB 2.0 480 Mbps protocol and data rate (hi-speed)
- Backward compatible to the USB 1.1 legacy protocol at 1.5 Mbps (low-speed) and 12 Mbps (full-speed)
- Can be connected with a Hi-Speed and OTG subsystem to perform as a standard Hi-Speed, Dual-Role Device (DRD), operating as either a fully USB 2.0 Hi-Speed compliant peripheral or an OTG host
- Minimal external component cost; USB 2.0 test mode support; Built-in self test features to confirm Hi-Speed, Full-Speed and Low-Speed operation
Deliverables
- Abstract LEF and Timing LIB Files
- Behavioral Verilog Model
- Assemble Guidelines
- Silicon Validation Report
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