The Digital Blocks DB-I2C-M-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 APB
System Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.
- I2C Master only with Parameterized FIFO:
- Targets embedded processors with high performance algorithm requirements, by independently controlling the Transmit or Receive of bytes of information:
- For Transmits, the processor writes the Slave Address & bytes of information into the FIFO, sets a start control bit, and waits for an interrupt or polls a status bit signaling completion
- For Receive, the processor writes the Slave Address into the DBI2C-M-APB, sets a start control bit, and waits for an interrupt or polls a status bit signaling completion. The processor then reads the bytes of information from the FIFO.
- Small VLSI footprint
- Master Controller Modes:
- Master – Transmitter
- Master – Receiver
- Multi-Master, Clock Synchronization, Arbitration, SCL held low by Slave, & Repeated Start capabilites
- Parameterized FIFO depth for higher performance. Optional 16 or 32-bit processor interface
- Supports two I2C bus speeds:
- Standard mode (100 Kb/s)
- Fast mode (400 Kb/s)
- Fast mode plus (1 Mbit/s)
- 8 sources of internal interrupts with masking control
- Compliance with AMBA 2.0 and I2C specifications:
- AMBA Specification (Rev 2.0), APB Bus
- Philips/NXP – The I2C-Bus Specification, Version 2.1, January 2000 and NXP Rev 0.3 19 June 2007
- Fully-synchronous, synthesizable Verilog or VHDL RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASIC design flows.
- The DB-I2C-M-APB Controller IP Core targets embedded processor applications with high performance algorithm requirements. While most I2C controllers require high processor interaction involvement, the DB-I2C-M-APB contains a parameterized FIFO and Smart Control for the processor to off-load the I2C transfer to the DB-I2C-M-APB Controller. Thus, while the DB-I2C-M-APB is busy, independently controlling the I2C Transmit or Receive transaction of data, the processor can go off and complete other tasks. Note that the Master only capability of the DB-I2C-M-APB adds to its small VLSI footprint requirements.
- Verilog or VHDL RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.