The DB-I2C-S-SCL-CLK is an I2C Slave Controller IP Core focused on low power, low noise ASIC / ASSP designs requiring the configuration & control of registers with no free running clock. The DB-I2C-S-SCL-CLK processes the I2C protocol & physical layers, and receives & transmits bytes with respect to the I2C payload to / from User Registers within an ASIC / ASSP / FPGA device.
The DB-I2C-S-SCL-CLK is a member of Digital Blocks DB-I2C Controller IP Core family, which includes I2C Master/Slave, I2C Master-only, and I2C Slave-only configurations.
- I2C Slave Controller - Implements Slave-only protocol for smaller VLSI footprint, for applications requiring Slave–Receiver and Slave–Transmitter capability
- SCL Clock only for low power, low noise applications requiring configuration & management of User Registers
- 7- or 10-bit addressing, General Call, SCL Low Wait States
- Supports five I2C bus speeds:
- Standard mode (100 Kb/s)
- Fast mode (400 Kb/s)
- Fast mode plus (1 Mbit/s)
- Ultra fast mode (5 Mbit/s)
- Hs-mode (3.4 Mbit/s)
- Compliance with I2C specifications:
- Philips – The I2C-Bus Specification, Version 2.1, January 2000
- NXP Rev .5 October 9, 2012
- Fully-synchronous, synthesizable Verilog RTL core. Easy integration into FPGA or ASIC design flows.
- The DB-I2C-S I2C Slave Controller IP Core targets embedded applications where the I2C Slave Controller connects to a bank of registers with SCL as the only clock, for low power, low noise applications.
- Verilog RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.
Block Diagram of the I2C Slave Controller - Low Power, Low Noise Config of User Registers