55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
JESD204
This IP core supports line rates of up to 12.5 Gbps characterized to the JESD204B specification and line rates up to 16.1 Gbps not characterized to the JESD204B specification and between 1-32 lane configurations. The IP Core can be configured as JESD204 Transmitter for interfacing to DAC device or JESD204 Receiver for interfacing to ADC device. The JESD204 IP core is delivered as a netlist along with the supporting wrapper files.
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Interface and Interconnect IP
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- Standard Compliant AMBA AHB SoC Interconnect, Soft IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
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- Physical Layer Interface Core
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