55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
LIN 2.2, 2.1 and 1.3 Protocol Controller IP
View LIN 2.2, 2.1 and 1.3 Protocol Controller IP full description to...
- see the entire LIN 2.2, 2.1 and 1.3 Protocol Controller IP datasheet
- get in contact with LIN 2.2, 2.1 and 1.3 Protocol Controller IP Supplier
Block Diagram of the LIN 2.2, 2.1 and 1.3 Protocol Controller IP IP Core
LIN Bus IP IP
- Local Interconnect Network (LIN) Soft Controller IP
- LIN Bus Master/Slave Controller Core
- LIN Bus Controller – Basic and Safety-Enhanced
- Configurable UART with FIFO, software and hardware flow control
- High Speed UART IP core - Universal Aysynchronous Receiver / Transmitter
- 8-bit FAST Microcontrollers Family