The DesignWare® ARC™ Processor Core AS 221BD is a configurable, extendible, dual core audio DSP optimized for high-performance audio applications. The processor is part of Synopsys’s HD Sound-to-Silicon solution Blu-ray players, Set-top boxes, Digital TVs and Media Servers all have one thing in common: they require high quality HD audio to accompany the HD video experience. Synopsys’s HD Sound-to-Silicon solution includes all components that enable highest quality audio processing: the licensable AS 221BD DSP, a broad portfolio of highly optimized audio codecs, and Synopsys’s DesignWare® Sonic Focus® audio enrichment technology. The DesignWare ARC Sound 221BD dual core processor is an audio-optimized digital signal processing subsystem for high-performance HD audio and Blu-ray Disc applications, that can be readily incorporated into multimedia SOCs. Subsystem Architecture:
Dual (2) digital signal processing (DSP) cores
Occupies 0.81mm2, including all caches and memories, in a 65nm LP process
Computational performance of 3.5GOPS at 350MHz
Fully software backward compatible with AS 211SFX and AS 210
Cross interrupts between cores for synchronization
Integrated Power Management Unit (PMU)
Chained JTAG for debug
Optional shared local memory
Digital Signal Processor core architecture:
5-stage instruction pipeline
32-bit data, instruction and address busses
XY memory and address generators eliminate memory fetches and additional CPU cycles
Dual 16x32 and 24x24 MAC
Zero overhead looping
Audio-optimized DMA unit
Configurable single-cycle instruction closely coupled memory (ICCM): 1KB ? 512KB
Configurable single-cycle data closely coupled memory (DCCM): 2KB ? 256KB
Configurable instruction cache: 2KB ? 32KB
Configurable data cache: 2KB ? 32KB
Software Support:
DTS HD MA
Dolby TrueHD
Dolby Digital (AC-3)
Dolby Digital Plus (E-AC-3)
aacPlus v1, v2 / HE AAC
MP3 LP
MPEG Layer I/II
LC SBC
MPEG MP3
MPEG-4 AAC-LC
MPEG-4 AAC-LC
Windows Media Audio 9 / 10Pro
G.726
FLAC
Vorbis
Monkey’s Audio
Sample Rate Conversion
Features
- Minimal core with cache configuration starts at 52,000 gates
- Fully configured inc
- DSP Inst., caches, ICU, etc at between 40-60K Gates
- Floating Point Extentions (Single and Double precission)
- Verious Hardware Multipliers and Dual Multiply Accumulation (Dual MAC) Units (Dual 16x16, Dual 16x32, 24x24, 32x32, etc...)
- Power consumption in 90nm between 24-50 uW/MHz
- 1.3 DMIPS/MHz x 2
Benefits
- A highly configurable and extandable RISC core
- Extendable with Customer acceleration logic and User-defined instruction
- Caches & closely coupled (single-cycle) memories
- 16-/32-bit Instruction Set Architecture for the smallest code size
Deliverables
- Delivered as synthesizable RTL source code (Verilog®), the DesignWare ARC 625D configurable core is fully compatible with industry standard design methodologies and tool flows
- ARChitect Correct-by-Construction Configuration GUI
- ARChitect Core Extensions Configuration GUI
- Standard & Custom Training
- Support & Maintenance
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