The CEVA-XC family of DSP cores features a combination of VLIW (Very Long Instruction Word) and Vector engines that enhance typical DSP capabilities with advanced vector processing. Based on the architecture of the CEVA-X DSP family, the CEVA-XC family of DSP cores incorporates up to four modular Vector Communication Units into the CEVA-X framework. The scalable CEVA-XC architecture offers a selection of highly powerful communication processors targeting the most demanding wireless applications and use cases, enabling software-defined modem design with minimal hardware. With its innovative programmable approach, the CEVA-XC family offers high flexibility that supports a large number of wireless standards on a single programmable platform, thereby significantly reducing development cost and time to market.
The third generation of the CEVA-XC family, the CEVA-XC4000, offers a series of six processors optimized for advanced communication applications. The CEVA-XC4000 delivers highly powerful vector capabilities alongside a powerful general computation engine supplying the performance and flexibility demanded by next generation communication applications.
- Fully programmable DSP processor architecture
- One, two or four vector processing units - each unit operates on 256-bit vector registers offering a powerful SIMD engine
- Up to 8 simultaneous instructions (8-Way VLIW)
- Efficient DSP support for non-vectorized data
- Efficient support for control and ANSI-C operations
- Extremely powerful computation capabilities
- Up to 128 16x16-bit MAC operations and/or 64 16x8-bit MAC operations
- Up to 128 arithmetic operations per cycle
- Over 800 16-bit operations in a cycle
- Exceptional power efficiency
- Incorporates a new Power Scaling Unit – PSU 2.0
- Dedicated power optimized Tightly Coupled Extensions (TCE)
- Enhanced power-optimized pipeline
- Scalable and configurable architecture for use in a wide range of wireless communication applications and devices through different processors, configurations and optional modules
- Scalable computation capabilities and memories
- Configurable utilization of optional instruction sets
- Uniquely designed for communication applications
- High flexibility SIMD programming model with intra-vector permutation capabilities
- Optimized modem instruction sets including high precision ISA, ML MIMO detectors, filtering, complex data permutations, and more
- Tightly Coupled Extenstions (TCE)
- A selection of coprocessor units allowing efficient low power implementation of demanding transceiver algorithms including: TD-FD transformation, ML MIMO detector, De-spreader and more
- User-defined coprocessor interface enabling customers to reuse their existing proprietary IP
- Offers parallel computing in parallel to the DSP functions
- Offloading the core and lowering its frequency to minimize power consumption
- Complete memory subsystem
- Includes tightly coupled memories (TCM), caches, AXI system interfaces, APB3 interface, advanced DMA controller, Fast Inter Connect (FIC) buses, message queues, emulation and profiling modules.
- Ensures easy integration and optimal performance in Target SoCs
- Integrates an innovative second generation Power Scaling Unit (PSU 2.0) offering significant energy savings for both battery-operated and stationary devices:
- Advanced power management for both dynamic and leakage power.
- Multiple voltage domains associated with the functional units.
- Multiple operational modes ranging from full operation, to debug bypass, to memory retention, to complete power shut-off (PSO).
Block Diagram of the Low-Power DSP Architecture Framework for the Widest Array of Advanced Wireless Standards