Centar's DFT circuit can perform all 35 transform sizes needed to implement the LTE SC-FDMA protocols. A number of unique architectural characteristics allow this programmable circuit to provide simultaneously high throughput, high SNQR, low power, and minimal use of LUTs and registers in an FPGA fabric. Programmability is derived from a new type of memory-based array implementation that avoids addressing conflicts. The number of cycles per DFT is reduced as a result of a novel matrix oriented algorithmic approach. Clock speeds are high (~400MHz for 65nm technology) because all computations are "localized", leading to reduced interconnect delays that are less than the logic cell delays. Short critical path lengths also lower power dissipation. Minimal numbers of LUT/registers are needed because the adaptive floating-point scaling scheme keeps word lengths much shorter than traditional fixed-scaling and block-floating point schemes. Altogether these features result in extremely efficient implementations.
- High Throughput: obtained from high clock rates (>400MHz using 65nm technology) and novel algorithms
- DFT size: runtime choice of sizes
- Programmability: new memory-based architecture provides for easy customization of DFT properties, functionality and I/O interface.
- Dynamic Range: combined block floating point and floating point architecture means smaller word lengths can be used for post processing operations such as equalization.
- Scalability: array based architecture means higher throughputs are obtained by increasing array size
- Power: array interconnects are entirely local, reducing parasitic routing capacitance to keep power dissipation low and clock speed high
- Implementation FPGA: Centar's DFT circuit can be used in any FPGA fabric containing embedded multipliers and memories.
- Data I/O: Normal order output data consisting of a mantissa plus an exponent, although a normalized, fixed-point output can be derived from this.
- Highest commercially available throughputs
- Minimal use of LUT and register FPGA fabric
- Programmability means circuit can be easily adapted to meet unique customer required functionality
- Netlist (e.g., for Altera FPGAs a verilog *.qxp file for synthesis or *.vo file for simulation)
- Synthesis constraints (e.g., for Altera FPGA’s an *.sdc file)
- Modelsim LTE SC-FDMA Testbench (*.vo file for DFT circuit plus verilog testbench control file) that reads data from input file and outputs transform data to output file. Also includes Matlab verification utilities
- Quartus LTE SC-FDMA Testbenches (35 DFT sizes, 12-points to 1296-points) that include pin-outs for use with an Altera Stratix III FPGA board development kit with (1) on-chip input/output data memories and a *.qxp file for the DFT circuit, that performs user selected number of blocks for a single size DFT; or (2) on-chip input/output data memories, verilog control circuitry, and a *.qxp file for the DFT circuit that cycles continuously through 2 blocks each of the LTE 35 different DFT sizes or (3) modelsim simulation environment of (2) using *.vo file.
- Matlab behaviorial bit-accurate model (p-code) for LTE SC-FDMA DFT sizes
- Documentation for above
- Nominal applications are LTE Single Channel DFT Frequency Division Multiple Access (SC-FDMA) based protocols.
- Other requiring non-power-of-two transform sizes
Block Diagram of the LTE Single Channel DFT Circuit IP Core