66 times faster than the original 80C51
5.5. times faster than the 80C251 - at the same frequency
The DQ80251 is a revolutionary, Quad-Pipelined, ultra high performance, speed optimized
soft core, of a 16-bit/32-bit embedded microcontroller. The core is fully configurable and allows selection of its features and peripherals, to create a dedicated system. It has been designed with a special concern for performance to power consumption ratio. This ratio is extended by an advanced power management PMU unit
. This product is built based on 14 years of DCD’s know-how, with triumphant 8051 architectures. The DQ80251 soft core is 100% binary-compatible with the industry standard 16-bit 80C251 and 8-bit 80C51 microcontrollers. There are two working modes of the DQ80251: BINARY (where original 80C51 compiled code is executed) and SOURCE (native 80C251 mode, using all DQ80251 performance). The DQ80251 has a built-in, configurable DoCD-JTAG on chip debugger, supporting Keil DK251 and standalone DoCD debug software. <font color="blue">Dhrystone 2.1 benchmark program runs 65.67 times faster than the original 80C51 and 5.5 times faster, than the original 80C251 at the same frequency.</font>
This performance can be also exploited to great advantage in low power
applications, where the core can be clocked over fifty times slower than the original implementation, with no performance penalty. Additionally, the compiled code size for SOURCE mode is about 2 times smaller
, comparing to an identical standard 8051 code, since DQ80251 instructions are more effective.
The DQ80251 is delivered with fully automated test bench
and complete set of tests
, allowing easy package validation at each stage of SoC design flow.
Each of the DCD's 80251 Core has a built-in support for the DCD Hardware Debug System, called DoCDTM
. Unlike other on-chip debuggers, the DoCDTM
provides non-intrusive debugging
of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. More details about DCD on Chip Debugger