Multi Protocol Endpoint IP Core for Safe and Secure Ethernet Network
Silterra 0.11um Ultra Low Leakage 6track Std Cell Library
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Silterra IP
- LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
- USB 2.0 On-chip oscillator, termination resistors, and DP/DM short circuit protection (0.18u)
- USB2.0 PHY, 8-bit or a 16-bit parallel interface, remaining backward compatible with USB1.1 legacy protocol at 12Mbps
- PHY layer solution for PCIe1.1/PCIe2.0 with a serial interface and PIPE3 compliant digital interface
- NVM MTP in Silterra (180nm)
- 400kHz Touch Sensor Silterra 0.18 μm