MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm, 12nm, N5)
SOF-Calibrated 48MHz USB Clock
The device implements a loop that controls the output frequency of a Current Controlled Oscillator (CC OSC) by means of an initial coarse-tuning followed by a fine-tuning.
The coarse tuning is based on an internal 1 kHz RC oscillator with accuracy better than 10%.
The Digital block adjust the CC OSC Output frequency through a 9-bit Current-Steering Digitalto-Analog converter until the 48 MHz Clock accuracy is sufficient for the USB Controller to generate valid Start-of-Frame (SOF) packets; it then fine-tune (and maintain) the Clock accuracy within 0.25%.
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