PCIe Gen2 is gaining popularity for it's flexibility, maturity, and ease of use, however many of our competitors implementations of the standard haven't been properly optimized for modern applications leading to battery drain, higher cooling costs, and lower end customer satisfaction.
The OmniPhy IP is architected with the mobile and tablet markets in mind - capable of very low power envelopes for very short interconnections. Designed on TSMC’s 28nm node, the OmniPhy PCIe Gen2 PHY is an optimized, differentiated IP.
OmniPhy is leading the charge towards a revitalized IP ecosystem, for mobile through it's proprietary implementation breakthroughs.
- PIPE compliant -> 8,10,16,20b bus widths
- Same design used for wire-bond or flip-chip packages
- The smallest footprint on the market
- Optimized for low-power, supporting all standard power saving modes
- Integrated PMA/PCS mates seamlessly to any compliant controller
- Customization to your unique metal-stack and/or foundry node requirement results in differentiation for you
- Industry leading DFT including high-speed SCAN, a full suite of analog and digital observation, production testing and loopback capability on-chip pattern generator and checker, and IEEE 1149.6 (AC) support
- Ease of integration – documentation and references covering all aspects of integration
- Integrated 2kV, 500V CDM, 200V MM ESD
- Smaller than our competitors (compare for yourself!)
- Dissipates less power
- Offers greater flexibility, now
- PCS RTL: PIPE compliant soft-IP with design constraints for physical implementation
- SerDes PMA behavioral model along with test benches for verification
- LEF abstracts for physical implementation
- Liberty Timing Views (.lib) for multi-corner timing analysis
- GDSII with DFM for high manufacturability
- DFT Models: Scan models for the hard-macro for ATE vector generation
- Documentation: Data Sheets, PCS MAS, RTL Application Notes, SerDes Layout Integration Guidelines, Package/Board guidelines, Test Plan, DFT Specifications