TSMC CLN40G 40nm Deskew PLL - 170MHz-850MHz

Features

• Designed to eliminate clock distribution latency in systems and individual chips.
• Precisely aligns the clock distribution output with a reference clock.
• Provides a zero-delay feedback divider and zero-skew divided clock outputs.

Deliverables

• GDSII (100% DRC and LVS clean)
• LVS Spice netlist
• Verilog model
• Synopsys synthesis model
• LEF for clock generator PLL
• User Guidelines including:
• integration guidelines,
• layout guidelines,
• testability guidelines,
• packaging guidelines,
• board-level