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USB 3.0 device controller

The USB 3.0 device controller IP is a high performance, highly configurable solution. It is fully customizable for your unique requirements.

Using a 64 bit data path, our highly parallel design ensures that:
•You can easily interface the IP to standard on-chip system buses with minimal wrapper logic
•Wider data path requires a lower clock frequency which leads to lower power consumption
•Lower core clock frequency also leads to easier and faster STA and back-end process.

Features

USB 3.0 Spec Compliant
Full support for low power features
PIPE complaint PHY interface
5Gbps transfer rate
62.5/125 MHz core controller clock frequency
Device Controller Features

Full support for Bulk, Stream, Isochronous as well as Interrupt Endpoints
Low power support
Full link power management support (U1, U2, U3)
Activity timeouts
Device and Host initiated wakeup
Wide 64 bit controller data path
Low controller clock frequency requirement (62.5 or 125 MHz) o Easy back-end
Fully configurable
Configurable number of endpoints
Configurable endpoint behavior
Configurable DMA engines
Configurable 64 bit/128 bit application side data interface
AHB friendly
Configurable buffer sizes
Can be targeted to ASIC as well as FPGA

FPGA Related Features

Low controller clock frequency leads to easy STA
Configurable buffer sizes can be easily mapped onto FPGA memories

Deliverables

Verilog Source code
Test-bench and Test suite
Behavioral Model for PHY
Documentation
Micro Architecture Document
Test-bench and Test plan along with description
IP core Integration Guide

Block Diagram of the USB 3.0 device controller

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