MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm, 12nm, N5)
IP Solutions Targeted for Ultra High Bandwidth
By Naveen Narang, Sr. IP Application Engineer at Open-Silicon
Posted on Tuesday Apr. 18, 2017
7:46 FlexE IP - A New flexible Ethernet client interface standard
2:24 Optimized ASIC Design Integrating High Speed SerDes
5:45 Smart City Gateway Platform
2:49 Interlaken IP : Ultra Scalable, High Speed, Serial Link-Based Chip-to-Chip Interface
1:58 Product Standardization: Death to a Growing Market
10:03 Moving Towards Design-Lite for Innovation
05:49