MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm, 12nm, N5)
SiliConch’s USB-C PD IP Solutions
By Shubham Paliwal, Logic Design Engineer of Siliconch
IP SoC 2017 Grenoble
December 6th-7th, 2017
Design and Reuse (D&R)
Posted on Wednesday Dec. 13, 2017