The AMBA 5 CHI Verification IP is ready-made for your environment, providing consistent results whether you are using Cadence Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have the freedom to build your testbench using any of these verification languages: SystemVerilog, e, Verilog, VHDL, or C/C++. Cadence Simulation VIP supports the Universal Verification Methodology (UVM) as well as legacy methodologies.
- The CHI VIP supports the AMBA® CHI Protocol.
- Enables Home, Request, Slave and Miscellaneous Node Design-Under-Test Configurations
- Includes Test Suite
- Supports monitoring and driving of all protocol Opcodes, including barrier, exclusive access, and DVM.
- Active HN-F, which generates snoop requests and response to RN-F commands (when interconnect is not present).
- Supports link, network and protocol layer communication
- Support for Rn-F/Rn-D/Rn-I to Hn-F/Hn-D/Hn-I/Mn and Hn-F/Hn-I/Mn to Sn-F/Sn-I
- Supports link, network and protocol layer communication, including flow control mechanisms, across all RnX-to-HnX and HnX-to-SnX links
- Models the cache in RnF-to-HnF link
- Each link can take the part of either node as an active agent generating requests/snoops and responding according to the requests sent its way, or as a passive agent monitoring protocol correctness and collecting functional coverage