The Simulation VIP is ready-made for your environment, providing consistent results whether you are using Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have the freedom to build your testbench using any of these verification languages: SystemVerilog, e, Verilog, VHDL, or C/C++. Simulation VIP supports the Universal Verification Methodology (UVM) as well as legacy methodologies.
- Industry's first M-PHY VIP
- Part of the broadest line of MIPI simulation VIP
- has been a MIPI Alliance Contributing Member since 2007
- The MPHY VIP supports MIPI M-PHY specification version 3.1 and below.
- Enables Master and Slave Design-Under-Test Configurations
- Provides PHY Only verification
- Includes Test Suite
- The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate.
- Complies with MIPI M-PHY 3.0 specification.
- Supports M-PHY Type 1 and Type 2.
- Supports serial interface (DpDn) and signaling interface (RMMI).
- Supports Burst state, ACTIVATED SAVE states (SLEEP and STALL) and hibernate (“HIBERN8”) state.