Industry Expert Blogs

Existing verification automation techniques – such as metric-driven verification, constrained-random test generation, and the Universal Verification Methodology (UVM) – have greatly eased block-level functional verification. But growing SoC complexity, both in terms of hardware and software, are calling for new approaches at the SoC and system levels. In this interview, Cadence fellow Mike Stellfox talks about the pros and cons of existing approaches and the need for new technology to facilitate use-case, software-driven verification.

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