A design methodology using Power-Grid Prototyping to optimize Area Performance of SoCs
By Abhishek Nigam (STMicroelectronics Pvt. Ltd), Anant Narain (Apache Design Solutions (a sub. of ANSYS Inc.))
Set-Top-Box(STB) SoC designs are extremely complex with multi-million standard cells, higher core utilization of around 70-80 %, and multiple clock domains including high and low frequencies. An assessment of any overdesign in the power grid of such SoCs becomes one of the key competitive business needs.
This paper first describes a methodology for power grid optimization leveraging early static IR flow and correlating with existing sign-off results. It also presents a methodology for doing early dynamic IR drop analysis, which can identify potential overdesigns in the grid to save valuable signal routing area. It outlines the impact of Metal6 power grid width variations on Static and dynamic IR drop using STB SoC in 40 nm Wire bond chip.
Finally, results and conclusion of changing metal density on static and dynamic IR drop analysis at early stage using ANSYS-Apache’s RedHawk tool are presented. The correlation of early results with final results observed are encouraging for decision-making in shrinking metal6 width to gain advantage in routing tracks and consequently floorplan change which can reduce the die-size - a value-add to SoC designs.