D&R Videos

Learn how to configure a PCIe IP with an AXI interconnect ... from PLDA Jan 28, 2020 4:44	Status Update of RISC-V P Extension Task Group from Andes Technology Corp. Jan 16, 2020 7:30	Discover how to configure XpressRICH IP from PLDA Nov 25, 2019 5:09
Powering RISC-V SoC With 1 To 1000s Cores from Andes Technology Corp. Nov 07, 2019 27:28	Cadence PCIe 4.0 Receiver JTOL Test from Cadence Oct 17, 2019 1:43	Verification with Emerging Memory Models from Cadence Oct 17, 2019 4:12
What is USB4? USB, PCIe, and DisplayPort with a Single ... from Synopsys Oct 15, 2019 2:12	An Introduction to Palladium Cloud from Cadence Aug 19, 2019 2:04	xSPI Standard Explained from Cadence Aug 06, 2019 3:42
The Storage Combo PHY IP - Nirvana! from Cadence Jul 24, 2019 2:41	What is Happening at the USB IF Standards Meetings? ... from Cadence Jul 17, 2019 4:03	Cloud-Hosted Design Solution - a Full-Service Cloud ... from Cadence Jul 10, 2019 2:37
Test, exercize and debug your PCIe add-in cards with ... from PLDA Jun 26, 2019 3:52	The Reason Why the Vision Q7 DSP Should be in Your ... from Cadence Jun 26, 2019 5:47	Passport Partners Program Expands Customer Cloud Deployment ... from Cadence Jun 20, 2019 4:36
Fast yet Low Power RISC-V Core IP for SoC Designers ... from Andes Technology Corp. Jun 17, 2019 20:20	Cadence Cloud - Fast, Painless, Proven Solutions for ... from Cadence Jun 12, 2019 7:08	Deep Dive on Simultaneous Localization and Mapping ... from Cadence Jun 06, 2019 5:25

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