Auto Clock Generation for a SoC
By Mrugesh Walimbe, Mahesh Penugonda (Open-Silicon)
This paper discusses a novel idea on automatic clocks generation for a SoC. A standard configurable input file has all the required clock requirements in a SoC given by the designer. A scripting language is used to parse the input file.
The script generates Synthesizable System Verilog RTL, System Verilog Assertions, Clock Constraints and Documentation in HTML format.
As the complexity of a SoC is growing in terms of
functionality and there are many requirements to generate different clock frequencies and associated clock requirements. At the same time the average SoC development schedule has shrunk. The SoC design challenges that are addressed in this paper include scalable clock design methodology, reduced human efforts/error, adherence to standard design practices, soft errors, low power controllability, reduced turnaround time for clock specification changes, enabling physical design process,
documentation aspects and reduced verification efforts.
This automation of Clock Generation results in quick implementation of clock requirements in a SoC.