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130nm OTP Non Volatile Memory for Standard CMOS Logic Process
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Synopsys Delivers 10X Performance in Formal Property Verification with Breakthrough Machine Learning Technology (Monday Aug. 27, 2018)
Synopsys today announced a state-of-the-art artificial intelligence (AI) enabled formal verification app, Regression Mode Accelerator, as part of the Synopsys VC Formal® solution.
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IBM and Synopsys Accelerate Post-FinFET Process Development with DTCO Innovations (Wednesday Aug. 15, 2018)
Synopsys, Inc. (Nasdaq: SNPS) today announced a collaboration with IBM to apply design technology co-optimization (DTCO) to the pathfinding of new semiconductor process technologies for post-FinFET technologies.
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Cadence Palladium Z1 Enterprise Emulation Platform Enables GUC to Accelerate SoC Design (Tuesday Aug. 14, 2018)
By combining the Palladium Z1 emulation platform with Cadence Xcelium™ Parallel Logic Simulation, GUC engineers were able to apply more complex SoC verification test scenarios with full debug visibility, accelerating verification by up to 795 times.
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Achronix and Mentor Partner to Provide Link Between High-Level Synthesis and FPGA Technology (Tuesday Aug. 07, 2018)
Achronix Semiconductor Corporation, a leader in field programmable gate array (FPGA)-based hardware accelerator devices and embedded FPGA (eFPGA) intellectual property (IP), today announced availability of an optimized High-Level Synthesis (HLS) flow from its partner, Mentor, a Siemens business, for its FPGA technology products.
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Thalia-DA and Catena confirm successful tape-outs of first analog IP re-use projects (Tuesday Jul. 31, 2018)
Thalia Design Automation and Catena, a leader in radio frequency (RF) communication intellectual property (IP) for connectivity, today announced successful completion of their first jointly delivered analog IP reuse projects.
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Cadence Introduces Voltus-XP Technology with Extensive Parallelism, Up to 5X Acceleration, and Increased Capacity for Power Signoff at Advanced Nodes (Monday Jul. 23, 2018)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that it has enhanced the Cadence® Voltus™ IC Power Integrity Solution with an extensively parallel (XP) algorithm option employing distributed processing technology for power grid signoff at advanced-node process technologies.
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Cadence Automotive Solution for Safety Verification Used by ROHM to Achieve ISO 26262 ASIL D Certification (Friday Jul. 13, 2018)
Cadence today announced that its Cadence® Automotive Solution has been used by ROHM CO., Ltd. for safety verification, a critical component of its ISO 26262-compliant tool chain for automotive LSIs.
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AMIQ EDA Announces its Design and Verification Tools Eclipse IDE Supports First Release of Accellera Portable Test and Stimulus Standard (PSS) (Thursday Jul. 12, 2018)
AMIQ EDA today announced its Design and Verification Tools (DVT) Eclipse IDE supports Portable Test and Stimulus Standard (PSS) 1.0 as released by Accellera Systems Initiative.
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Cadence JasperGold Formal Verification Platform Enables Hitachi to Develop Measures for Fault Avoidance to Comply with IEC 61508 Series SIL 4 Requirements (Monday Jul. 09, 2018)
Cadence today announced that Hitachi, Ltd. has used the Cadence® JasperGold® Formal Verification Platform to develop νCOSS® S-zero®, an industrial facilities functional safety controller that has been certified for Safety Integrity Level (SIL) 3 in accordance with the International Electrotechnical Commission® (IEC) 61508 Series functional safety standard.
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Cadence Full-Flow Digital and Signoff Tools Certified on Samsung Foundry's 7LPP Process Technology (Tuesday Jul. 03, 2018)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its full-flow digital and signoff tools have achieved certification for Samsung Foundry’s 7-nanometer (nm) Low Power Plus (LPP) process technology.
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Mentor extends support of tools and solutions for Samsung Foundry's 8LPP and 7LPP process technologies (Wednesday Jun. 27, 2018)
Mentor, a Siemens business, today announced it has enabled a wide range of Mentor verification tools and solutions for the latest versions of Samsung Foundry's 8LPP and 7LPP offerings.
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Cadence Perspec System Verifier Supports New Accellera Portable Test and Stimulus Specification 1.0 (Wednesday Jun. 27, 2018)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that the Cadence® Perspec™ System Verifier supports the new Accellera Portable Test and Stimulus Specification (PSS) 1.0 released by the Accellera Systems Initiative.
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Sankalp Semiconductor Announces Availability of Automated Analog Validation Services Environment - SAVE (Tuesday Jun. 26, 2018)
Sankalp Semiconductor, a design service company offering comprehensive digital & mixed signal SoC services and solutions, today at 55th DAC 2018 announced the availability of Sankalp Automated Validation Environment (SAVE).
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Cadence Delivers the First Broad Cloud Portfolio for the Development of Electronic Systems and Semiconductors (Monday Jun. 25, 2018)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today launched the Cadence® Cloud portfolio, the first broad cloud portfolio for the development of electronic systems and semiconductors.
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Synopsys RedHawk Analysis Fusion Certified for Samsung Foundry's 10LPE, 8LPP, 7LPP Advanced-Node Designs (Monday Jun. 25, 2018)
Synopsys, Inc. (Nasdaq: SNPS) today announced continued momentum in the rollout of RedHawk™ Analysis Fusion technology through certification by Samsung Foundry.
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Synopsys Custom Design Platform Accelerates Robust Custom Design for Samsung Foundry's 7LPP Process Technology (Monday Jun. 25, 2018)
Synopsys today announced that Samsung Electronics has certified the Synopsys Custom Design Platform for Samsung Foundry's 7-nanometer (nm) Low Power Plus (LPP) process Samsung Foundry's 7LPP is its first semiconductor process technology to use extreme ultraviolet (EUV) lithography, a state-of-the-art process technology that greatly reduces complexity and offers significantly better yield and fast turnaround time when compared to its 10-nanometer (10nm) FinFET predecessors.
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Cadence Collaborates with Amazon Web Services to Deliver Electronic Systems and Semiconductor Design for the Cloud (Monday Jun. 25, 2018)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced it is collaborating with Amazon Web Services (AWS) to deliver electronic systems and semiconductor design with the Cadence® Cloud portfolio.
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Synopsys' ASIP Designer Tools Enables RIKEN to Successfully Develop Application-Specific Instruction-Set Processor in Less Than Six Months (Monday Jun. 25, 2018)
Synopsys today announced that RIKEN successfully developed its high-performance application specific instruction set processor (ASIP) core for its molecular dynamics (MD) simulator using Synopsys' ASIP Designer tool.
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Cadence and Microsoft Collaborate to Facilitate Semiconductor and System Design on the Microsoft Azure Cloud Platform (Monday Jun. 25, 2018)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced a collaboration with Microsoft to facilitate electronic systems and semiconductor design with the Cadence® Cloud portfolio.
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Vatics Standardizes on Synopsys' Fusion Technology for its Next-Generation Multimedia SoC Design (Friday Jun. 22, 2018)
Synopsys today announced that Vatics, Inc., a trusted leader in advanced multimedia technologies, has adopted Synopsys' Fusion Technology™ for its next-generation multimedia system-on-chip (SoC) design.
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Synopsys Delivers PrimePower Power Analysis to Accelerate Robust SoC Design (Thursday Jun. 21, 2018)
Synopsys today introduced PrimePower, an expanded power analysis solution created to accelerate system-on-chip (SoC) design closure by extending signoff power analysis to drive early design implementation and accurate reliability analysis.
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Synopsys Unveils Next-Generation ZeBu Server 4 (Monday Jun. 18, 2018)
ZeBu Server 4 builds on the proven ZeBu Fast Emulation architecture with 2X the emulation performance over competing emulation solutions, to enable system-on-chip (SoC) verification and software bring-up, and to address the exploding verification requirements of automotive, 5G, networking, artificial intelligence (AI), and datacenter SoCs.
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Synopsys Fusion Technology Enables Lower Power, Smaller Area, and Higher Performance on Samsung Foundry 7LPP Process with EUV (Thursday Jun. 14, 2018)
Synopsys, Inc. (Nasdaq: SNPS) today announced that Samsung Foundry has certified the Synopsys Design Platform with Fusion Technology for 7-nanometer (nm) Low Power Plus (LPP) process with Extreme Ultraviolet (EUV) lithography technology.
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Synopsys IC Validator Certified by Samsung Foundry for 7nm Signoff Physical Verification (Thursday Jun. 14, 2018)
Synopsys, Inc. (Nasdaq: SNPS) today announced that Synopsys' IC Validator has been certified by Samsung Foundry for signoff of all designs using its 7-nanometer (nm) Low Power Plus (LPP) process with Extreme Ultraviolet (EUV) lithography technology.
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Xpeedic's IRIS Certified for EM Simulation in GLOBALFOUNDRIES 22FDX Process (Wednesday Jun. 13, 2018)
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Baum Launches New Version of Power Modeling, Analysis Solutions for Hardware Design (Tuesday Jun. 12, 2018)
Baum Inc. today launched the latest version of its flagship product PowerBaum, a state-of-the-art, high-speed and accurate power modeling and analysis solution for engineering groups to fully optimize the energy efficiency of their hardware designs.
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Breker Verification Systems Unveils Next-Generation Trek5 with Fully Compliant Support for Accellera Portable Stimulus Standard (Tuesday Jun. 12, 2018)
Breker Verification Systems today unveiled the latest version of its Trek portfolio and announced full compliance with release 1.0 of the Portable Stimulus Specification (PSS) from Accellera.
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Mentor Veloce hardware emulation platform now available on Amazon Web Services (Monday Jun. 11, 2018)
Mentor, a Siemens business, today announced that the Veloce® Strato platform is now a customer-validated cloud computing emulation platform directly accessible on-demand on Amazon Web Services (AWS).
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Real Intent Awarded U.S. Patent for Methods and Systems for Correcting X-pessimism in Gate-level Simulation or Emulation (Friday Jun. 08, 2018)
Real Intent Inc. has been awarded U.S. patent 9,965,575 for methods and systems for correcting X-pessimism in gate-level simulation or emulation.
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Intento Design Cooperates with STMicroelectronics to Accelerate Analog Design and Migration of FD-SOI Chips at Functional Level (Thursday Jun. 07, 2018)
Intento Design has announced its collaboration with STMicroelectronics (ST) in pushing forward its ID-XploreTM EDA software aimed to solve the critical design challenges in the FD-SOI process nodes.