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Turnkey UWB MAC and PHY platform IP, for FiRa 2.0, CCC Digital Key 3.0, and Radar
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Intento Design Cooperates with STMicroelectronics to Accelerate Analog Design and Migration of FD-SOI Chips at Functional Level (Thursday Jun. 07, 2018)
Intento Design has announced its collaboration with STMicroelectronics (ST) in pushing forward its ID-XploreTM EDA software aimed to solve the critical design challenges in the FD-SOI process nodes.
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Synopsys Delivers AI-enhanced Digital Design Platform Bringing Artificial Intelligence to Design Implementation (Tuesday Jun. 05, 2018)
Synopsys today announced it has been enhancing its industry-premier design tools with state-of-the-art artificial intelligence (AI) technology to address the extreme complexities of leading-edge design.
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Cadence Full-Flow Digital and Signoff Tools and Verification Suite Provide Optimal Results for 7nm Arm Cortex-A76 CPU Designs (Friday Jun. 01, 2018)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its full-flow digital and signoff tools and the Cadence® Verification Suite support the new Arm® Cortex®-A76 processor for laptops and smartphones.
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Synopsys Enables Tapeout Success for Early Adopters of Arm's Latest Premium Mobile IP, Including Cortex-A76 and Mali-G76 Processors (Thursday May. 31, 2018)
Synopsys today announced that early adopters of Arm's latest premium mobile platform, including Arm® Cortex®-A76, Cortex-A55, and Arm Mali™-G76 processors, have successfully taped out SoCs using Synopsys' Design Platform with Fusion Technology™, Verification Continuum™ Platform, and DesignWare® Interface IP.
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Toshiba Memory Corporation and Synopsys Collaborate to Accelerate 3D Flash Memory Verification (Wednesday May. 30, 2018)
Synopsys today announced that it has collaborated with Toshiba Memory Corporation to accelerate the verification of Toshiba Memory Corporation's BiCS FLASH™ vertically stacked three-dimensional (3D) flash memory.
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Real Intent's New Verix SimFix Software Delivers First Intent-Driven Remedy for Verification Pessimism (Wednesday May. 30, 2018)
Real Intent today launched Verix SimFix, the first intent-driven verification remedy for gate-level simulation (GLS) of digital designs. Verix SimFix automatically eliminates X-pessimism, the major obstacle to successful GLS and boosts productivity for SoC design teams.
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Andes Technology Corporation and XtremeEDA Corporation Cooperate to Develop Joint Design Wins on Emerging RISC-V Designs (Thursday May. 24, 2018)
Andes to Offer Its Low-Power, High Performance CPU Cores, Including New RISC-V IP; XtremeEDA to Provide Its Front-end IC Design Expertise to Reduce Designers’ Time to Market
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Cadence Full-Flow Digital and Signoff Tools Certified on Samsung's 8LPP Process Technology (Wednesday May. 23, 2018)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its full-flow digital and signoff tools have achieved certification for Samsung Foundry’s 8-nanometer (nm) Low Power Plus (LPP) process.
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Synopsys Design Platform Certified for Samsung 8LPP Process Technology (Wednesday May. 23, 2018)
Synopsys today announced that Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, has certified the Synopsys Design Platform for Samsung Foundry's 8-nanometer (nm) LPP (Low Power Plus) process.
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Synopsys IC Validator Certified by GLOBALFOUNDRIES for Signoff Physical Verification (Monday May. 14, 2018)
Synopsys today announced that GLOBALFOUNDRIES (GF) has certified the Synopsys IC Validator tool for physical signoff on the GF 14LPP process technology.
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Cadence Innovus Implementation System Speeds Development of New Realtek DTV SoC Solution (Thursday May. 03, 2018)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Realtek Semiconductor Corp. used the Cadence® Innovus™ Implementation System for its 28nm Digital TV (DTV) System-on-Chip (SoC) production tapeout and achieved an area improvement and reduced power.
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Mentor enhances tool portfolio for TSMC 5nm FinFET and 7nm FinFET Plus processes and Wafer-on-Wafer stacking technology (Wednesday May. 02, 2018)
Mentor, a Siemens business, has announced that several tools in its Calibre® nmPlatform and Analog FastSPICE (AFS™) Platform have been certified by TSMC for the latest versions of TSMC’s 5nm FinFET and 7nm FinFET Plus processes.
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Imperas and Andes Extend Partnership, Delivering Models and Virtual Platforms for Andes RISC-V Cores with New AndeStar V5m Extensions (Tuesday May. 01, 2018)
Imperas Software and Andes Technology today announced Open Virtual Platforms™ (OVP™) models and virtual platform support for powerful new extensions in the AndesCore™ N25 and NX25 IP processors, which are AndeStar™ V5 32-bit and 64-bit architectures based on the RISC-V technologies.
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Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation (Tuesday May. 01, 2018)
Cadence today announced its continued collaboration with TSMC to further 5nm and 7nm+ FinFET design innovation for mobile and high-performance computing (HPC) platforms.
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Cadence Supports New TSMC WoW Advanced Packaging Technology (Tuesday May. 01, 2018)
Cadence today announced that its full suite of Cadence® digital, signoff and custom/analog IC design tools, along with advanced IC packaging design solutions, support the new TSMC Wafer-on-Wafer (WoW) stacking technology.
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TSMC Certifies Synopsys Design Platform for High-performance 7-nm FinFET Plus Technology (Monday Apr. 30, 2018)
Synopsys today announced certification of the Synopsys Design Platform with TSMC's latest Design Rule Manual (DRM) for advanced 7-nanometer (nm) FinFET Plus process technology.
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Synopsys Digital and Custom Design Platform Certified for TSMC's Most Advanced 5-nm Process Technology for Early Design Starts (Monday Apr. 30, 2018)
Synopsys today announced the certification of its Synopsys Design Platform for early design starts on TSMC's latest version of its most advanced 5-nanometer (nm) process technology. Enabled through close and early collaboration with TSMC, the IC Compiler™ II place-and-route solution deploys next-generation placement and legalization technologies to co-maximize routability and overall design utilization.
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Exostiv Labs now supports Intel Stratix 10 FPGA (Monday Apr. 23, 2018)
Exostiv Labs has released a major update of its Exostiv Dashboard software, that includes the support of Intel Stratix 10 FPGA family.
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IEEE Publishes Standard Revision for SystemVerilog - Unified Hardware Design, Specification and Verification Language (Thursday Apr. 19, 2018)
IEEE, the world's largest technical professional organization dedicated to advancing technology for humanity, and the IEEE Standards Association (IEEE-SA), today announced the publishing and availability of the standard revision IEEE 1800—SystemVerilog – Unified Hardware Design, Specification and Verification Language.
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Cadence Expands Virtuoso Platform with Enhanced System Design, Advanced Node Support down to 5nm, and Simulation-Driven Layout (Wednesday Apr. 11, 2018)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today introduced major enhancements to its Cadence® Virtuoso® custom IC design platform that improve electronic system and IC design productivity.
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eVaderis collaborates with Mentor on accelerating eMRAM IPs and Compilers development (Monday Mar. 26, 2018)
eVaderis, the worldwide leader company offering innovative IP solutions based on new disruptive embedded NVM, has announced today that it has joined Mentor®, a Siemens Business’ OpenDoor® Program to build advanced design solutions for embedded non-volatile (NVM) MRAM technology.
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Synopsys Accelerates Development of Renesas R-Car V3H SoC that Achieves Cutting-edge Computer Vision (Wednesday Mar. 21, 2018)
Synopsys today announced it has worked with Renesas Electronics to contribute to the development of Renesas' latest R-Car V3H system-on-chip (SoC).
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Synopsys Announces Industry's Most Comprehensive Automotive ISO 26262 Certification for Design Platform (Tuesday Mar. 20, 2018)
Synopsys today announced the industry's most comprehensive independent ISO 26262 functional safety assessment and certification for all the tools in the Synopsys Design Platform, enabled by Synopsys' Fusion Technology™.
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Synopsys Introduces Breakthrough Fusion Technology to Transform the RTL-to-GDSII Flow (Tuesday Mar. 20, 2018)
Synopsys today unveiled its breakthrough Fusion Technology that transforms the RTL-to-GDSII design flow with the fusion of best-in-class optimization and industry-golden signoff tools, enabling designers to accelerate the delivery of their next-generation designs with industry-best full-flow quality-of-results (QoR) and the fastest time-to-results (TTR).
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Synopsys Enables Robust Design Optimization for Next-generation High-performance Computing, Mobile and Automotive Products with IC Compiler II and RedHawk Analysis Fusion (Tuesday Mar. 20, 2018)
Synopsys, in collaboration with ANSYS, today announced the immediate availability of RedHawk™ Analysis Fusion, a complete in-design power integrity add-on solution for Synopsys IC Compiler™ II place-and-route system users.
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Synopsys Advances Custom Platform to Accelerate Robust Custom Design (Monday Mar. 12, 2018)
Synopsys today announced release of the latest versions of its circuit simulation and custom design products—HSPICE®, FineSim® SPICE, and CustomSim simulators and the Custom Compiler™ IC design tool—to address the growing need for robust custom design.
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CSEM selects ID-Xplore to accelerate analog design and technology porting at functional level (Monday Mar. 12, 2018)
Intento Design and CSEM announce that CSEM has selected ID-Xplore™ to accelerate its analog design process and allow its designers to perform technology porting seamlessly at the functional level.
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Imec and Cadence Tape Out Industry's First 3nm Test Chip (Wednesday Feb. 28, 2018)
imec and Cadence today announced that its extensive, long-standing collaboration has resulted in the industry’s first 3nm test chip tapeout.
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Magillem Partners with Imperas (Monday Feb. 26, 2018)
Together, Magillem and Imperas provide a unique virtual prototyping solution set, fully based on the IEEE standards IP-XACT and SystemC.
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AMIQ EDA Announces its Design and Verification Tools Eclipse IDE Supports Cadence Perspec System Verifier using System Level Notation (Monday Feb. 26, 2018)
AMIQ EDA today announced its Design and Verification Tools (DVT) Eclipse IDE supports the System-Level Notation (SLN) portable stimulus syntax developed by Cadence® Design Systems, Inc.