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Thursday, May 8, 2025

• The future of AI runs on the GPU
• $50m quantum computing lab for Paris
• Tensilica AI co-processor for automotive
• Cadence and AVCC to Advance Physical AI Innovations for Autonomous Vehicles
• Xylon at ADAS&AVT Expo Europe 2025
• Xylon Introduces Xylon ISP Studio
• Kyocera Licenses Quadric's Chimera GPNPU AI Processor IP
• Axiomise Featured Gold Sponsor at RISC-V Summit Europe Next Week in Paris
• Cadence Accelerates Physical AI Applications with Tensilica NeuroEdge 130 AI Co-Processor

Wednesday, May 7, 2025

• Imec and TNO open Holst Centre Photonics Lab at High Tech Campus
• Rapidus Starts Path to Advanced Chipmaking in Japan Government-backed startup's 2-nanometer pilot production gets underway
• AI vs. AI: Both Friend and Foe in Cybersecurity
• €15m for European image sensor breakthrough
• Cybord's Visual AI solution to be integrated with Siemens' Opcenter MES
• Keysight Expands USB Standards Support in System Designer for USB
• MIPI C-PHY v3.0 Adds New Encoding Option to Support Next Generation of Image Sensor Applications
• EDA Companies Throw Support Behind TSMC's New A14 Process
• Agile Analog appoints CEO to drive growth
• Numem Appoints Former Intel Executives to Leadership Team
• Optimized SAR ADCs, Sigma-Delta ADCs, DACs, and Audio CODECs for IoT, MCU, SoC, and Consumer Applications

Tuesday, May 6, 2025

• Excelliance MOS Adopts Silvaco DTCO Flow for the Development of Next-Gen Silicon Carbide Devices
• AMD Reportedly Drops Samsung Foundry in Favor of TSMC's 4nm Production in Arizona
• Synopsys slides into design enablement role in quantum computing
• Boss Semiconductor's CEO Park Jae-hong aims to disrupt Qualcomm's automotive chip dominance
• Agile Analog appoints CEO to drive growth
• Enabled on makeChip and powered by Racyics, the SpiNNaker2 chip forms the core of the newly launched SpiNNcould supercomputer!
• Semidynamics Announces Cervell™ All-in-One RISC-V NPU Delivering Scalable AI Compute for Edge and Datacenter Applications
• CELUS Design Platform integrates with Cadence's OrCAD X Platform

Monday, May 5, 2025

• Global Semiconductor Sales Increase 18.8% in Q1 2025 Compared to Q1 2024; March 2025 Sales up 1.8% Month-to-Month
• UK Digital Twin Centre opens in Belfast to drive nationwide industrial innovation

Sunday, May 4, 2025

• Andes Voyager RISC-V Micro-ATX Board Seeing Patches For Mainline Linux Support
• TSMC leads Taiwan's patent filings in Q1 2025

Thursday, May 1, 2025

• IBM Cloud is First Service Provider to Deploy Intel Gaudi 3
• Silvaco Partners with Kyung Hee University's Professor Jin Jang on AI-Powered Fab Technology Co-Optimization for Next Generation Display Technologies
• Ensuring IoT Designs Comply With the Cyber Resilience Act—and Are Seen to Do So
• Thalia enhances AMALIA Platform with new AI models to revolutionize analog, RF and mixed-signal IC design migration
• Intel Foundry Gathers Customers and Partners, Outlines Priorities
• Movellus Debuts Industry-First On-Die Power Delivery Network Analyzer
• Weebit Nano Q3 FY25 Quarterly Activities Report

Wednesday, April 30, 2025

• Enabling the next generation of smart glasses
• IC'Alps joins Intel Foundry Accelerator program as Value Chain Alliance (VCA) and Design Services Alliance (DSA) partner
• Intel tweaks its 18A process with variants tailored to mass-market chips, big AI brains
• Weebit Nano and DB HiTek to demonstrate chips integrating Weebit ReRAM at PCIM 2025
• EU likely to miss 2030 microchip target
• Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
• SkyeChip Joins Intel Foundry Accelerator IP Alliance
• Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
• Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
• Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
• Imec coordinates EU Chips Design Platform
• CFX 0.13μm eFuse OTP IP has been applied in the mass production of over 15,000 CMOS image sensors

Tuesday, April 29, 2025

• Award-winning, Nordic-powered outdoor asset tracker supports sustainable logistics
• Silvaco Expands Product Offerings in Photonics and Wafer-Scale Plasma Modeling for AI Applications with Acquisition of Tech-X Corporation
• Keysight EDA and Intel Foundry Collaborate on EMIB-T Silicon Bridge Technology for Next-Generation AI and Data Center Solutions
• Spain launches €800m quantum strategy
• QuickLogic to Report First Quarter Fiscal 2025 Financial Results on Tuesday, May 13
• Cadence to Buy Artisan to Support Chiplet, 3D IC Future
• European AI processor developer gets €40m for manufacturing
• VSORA Raises $46 Million to Bring World's Most Powerful AI Inference Chip to Market
• Codasip launches complete exploration platform to accelerate CHERI adoption
• BrainChip Collaborates with Chelpis-Mirle on Security Solution
• VeriSilicon Launches the Industry-Leading Automotive-Grade Intelligent Driving SoC Design Platform
• New Audio Sample Rate Converter (ASRC) IP Core from CAST Offers Versatility with High Fidelity
• UK grants 2D semiconductor research £6 million
• Thalia enhances AMALIA Platform with new AI models to revolutionize analog, RF and mixed-signal IC

Monday, April 28, 2025

• Premier ASIC and SoC Design Partner Rebrands as Aion Silicon
• Faraday Adds QuickLogic eFPGA to FlashKit-22RRAM SoC for IoT Edge
• NEXT Semiconductor Technologies Collaborates with BAE Systems to Develop Next Generation Space-Qualified Chips
• Wi-Fi 7 (802.11be) RF Transceiver IP Core Ready for High Speed Wireless Connectivity Applications
• Premier ASIC and SoC Design Partner Rebrands as Aion Silicon
• Baya Systems, Imagination Technologies and Andes Technology to Present on Heterogeneous Compute Architectures at Andes RISC-V CON Silicon Valley
• Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
• Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
• QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip