Turnkey UWB MAC and PHY platform IP, for FiRa 2.0, CCC Digital Key 3.0, and Radar
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IP / SOC Products News
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SafeNet Announces Inline IPSec Security Engine for System on Chip Designs; Silicon-Proven IP Enables OEMs to Build Gigabit VPN Security into High Performance Processors (Wednesday Jan. 25, 2006)
The SafeXcel IP Inline Security Engine takes a significant step beyond traditional SoC security architectures with micro-programmed hardware for intensive packet classification, filtering, and flow processing for every packet. The result is superior data
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ARM Processor and Physical IP deliver groundbreaking 750 MHz ARM11 Implementation (Wednesday Jan. 25, 2006)
The optimized implementation delivers an industry-leading performance of more than 920 Dhrystone MIPS for existing applications and operating systems without the need for expensive software re-design or re-compilation.
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Evatronix SA successfully completes High-Speed USB On-The-Go compliance testing procedure for its USB OTG controller core (Wednesday Jan. 25, 2006)
The reference design submitted for compliance testing of the USBHS-OTG-SD-S core was a mass storage class design, implementing host and device operation modes and consisting with a handful of Evatronix IP cores (including R80515 8-bit microcontroller core
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Synopsys DesignWare IP Enables Next-Generation PCI Express 2.0 Products (Tuesday Jan. 24, 2006)
Synopsys is First to Deliver PCI Express Gen II Digital IP for Increased Bandwidth in Networking, Embedded and Computer Applications
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CEVA Announces First Available Silicon of Mobile-Media2000 Solution for High-End Mobile Multimedia Applications (Tuesday Jan. 24, 2006)
Silicon-Proven DSP-Based Mobile-Media Platform Offers Complete Set of Multimedia Codecs, Including H.264 Encoding and Decoding up to D1 Resolution
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Toshiba Adds Multi-Protocol High-Speed SERDES I/O Core Family That Meets High Speed Requirements of Storage, Networking, Consumer and Gaming Markets (Tuesday Jan. 24, 2006)
Designed in the Toshiba 90nm Process for Small Silicon Footprint and Reduced Cost; Scalable for More than 64 Ports of Fibre Channel
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SNOWBUSH microelectronics Announces 10-Bit, 140 MSPS, ADC IP Core in Foundry Standard 0.18 um CMOS Process (Monday Jan. 23, 2006)
High Speed ADC Responds to the Needs of Power Line Networking, Wireless Networking, Data Acquisition and Video Graphics Markets
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Innovative Silicon Inc. Announces Silicon Validation of Z-RAM Technology (Monday Jan. 23, 2006)
Z-RAM Proven Far More Resistant to Soft Errors Than SRAM Technologies
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Sun Microsystems Launches OpenSPARC Project - Ignites New Open Source Community for Breakthrough UltraSPARC T1 Processor (Wednesday Jan. 18, 2006)
Sun Open Sources Microprocessor Design, Lowering Barriers to Innovation and Application Development for First Purpose-Built Processor for the Next Internet Build-Out
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Arasan Demonstrates World's First SD / SDIO Host Ver 2.00 IP Core with Advanced DMA (Monday Jan. 16, 2006)
The Ver 2.00 compliant Standard SD Host supports the Advanced DMA function which reduces the protocol overhead and improves throput. The IP has already been delivered as the standard release to recent customers and as an upgrade to existing customers
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Sidense offers One-Time-Programmable (OTP) macro in UMC's 130nm Logic CMOS process (Monday Jan. 09, 2006)
Sidense’s OTP memory macros do not require any additional masks or process steps, and utilize only one transistor as a memory cell, positioning it as a leader in area efficient, secure, and low power, NVM IP core solutions.
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Nero Demonstrates AVC/H.264 High Profile Decoding IP Core at CES 2006 (Friday Jan. 06, 2006)
Nero, leaders in digital media technology, announced today the availability of its new Nero Digital(TM) AVC/H.264 video decoder VHDL IP core. The perfect solution for ASICs and SoCs is hardware-based and capable of full ISO/IEC 14496-10 Advanced Video Cod
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MediaWorks Unveils MediaFlex(TM) Platform Architecture, Enabling Next Generation Of Digital Video Products (Thursday Jan. 05, 2006)
Programmable, low power SoC platform offers manufacturers flexibility, fast time-to-market and low system cost First reference designs for PMPs and recorders now available
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EVE Offers Catalog of High-Performance Peripheral IP to Address Wireless, Graphics/Video/Multimedia, Networking, Processor Markets (Thursday Jan. 05, 2006)
Memory, Transactor, Hardware Bridges Components Designed to Support EVE's ZeBu
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Tokyo Electron Device Expands Business Globally with Advanced Secure Digital (SD Memory / SDIO Card) Controller Technology (Wednesday Jan. 04, 2006)
Tokyo Electron Device Licenses Advanced SD/SDIO Host and Card-Side Controllers To Enable High-Performance SD Memory / SDIO Card Devices
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SigmaTel Expands IP Licensing Program with Acquisition of Original MP3 Player Patents; Newly Expanded Global Licensing Strategy Targeted at MP3 Silicon and MP3 Player Manufacturers (Wednesday Jan. 04, 2006)
The licensing program is focused on IP used in MP3 players or in portable audio System on Chip (SoC) solutions for MP3 players and covers patents that SigmaTel has been awarded or has acquired in China, Korea, Europe and the United States
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Imagination Technologies Launches Ground-Breaking High-Definition Video Decoder Technology; HD-Video Core and Wide Range of Image Enhancement IP Redefine HD Capabilities (Tuesday Jan. 03, 2006)
Imagination Technologies key HD IP core, PowerVR MSVDX, is a multi-standard high definition video decoder core enabling HD-DVD / Blu-ray decode and HD-Broadcast reception with maximised video-quality.
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Imagination Technologies Shows Silicon-Based Mobile TV Receiver IP Platform at CES 2006 (Tuesday Jan. 03, 2006)
Wide Range of Multi-standard Mobile Video IP Also On Display
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LTRIM's Micropower LDO IP Blocks Increase Battery Life (Thursday Dec. 22, 2005)
Low quiescent current and fast response increase operating time for handhelds
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MorethanIP, announces several new cores for the Ethernet application space for proprietary 2.5 Gbps Ethernet and an improved Ethernet Switch Core with quality of service support (Thursday Dec. 22, 2005)
MorethanIP, announces several new cores for the Ethernet application space for proprietary 2.5 Gbps Ethernet and an improved Ethernet Switch Core with quality of service support
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MoSys and Open-Silicon Pound Tharas Systems Design Into Production; Tharas Systems Hammer(R) Verification Appliances Powered by Large Number of High-Speed 1T-SRAM Memory (Tuesday Dec. 20, 2005)
Tharas Systems Hammer(R) Verification Appliances Powered by Large Number of High-Speed 1T-SRAM Memory
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Synopsys Expands Mixed-Signal IP Portfolio With Interface Cell Libraries Featuring DDR2 SDRAM I/Os (Wednesday Dec. 14, 2005)
Provides Complete Set of Standards-Based I/O Libraries for General Purpose and High-Performance Applications
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VinChip Systems announces successful silicon validation of Embedded USB 2.0 Host Controller by Myson Century (Wednesday Dec. 14, 2005)
Myson Century a leader in Flat Panel Display Technologies confirmed that it has successfully completed Silicon Validation VinChip USB 2.0 Embedded Host Controller
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Hitachi and Renesas Technology Develop Low-Power MOS Phase-Change Memory Cells for On-Chip Memory of Microcontrollers (Tuesday Dec. 13, 2005)
The new cell, which can be programmed at a 1.5V power supply voltage with only a 100µA programming current, is a promising solution for the on-chip nonvolatile memory of next-generation microcontrollers for embedded systems
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Cadence Delivers New RF Design Kit Targeting Customer Design Challenges in Wireless (Monday Dec. 12, 2005)
Latest Kit Continues Cadence Execution on Strategy to Address Key Vertical Market Applications
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Ambarella Launches Industry's First HD H.264 System-on-Chip for Hybrid Digital Cameras (Monday Dec. 12, 2005)
Venture-backed Start-up Sets New Standard for the High Definition Experience with Low Power, Cost-effective Platform
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Silicon Logic Engineering's SPI-4 Phase 2 IP Core Integrates Easily (Thursday Dec. 08, 2005)
SLE’s SPI-4.2 is available in 9 different technologies and easily portable to new technologies. SLE’s SPI-4.2 has been used in over 25 different chips to date.
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Synopsys Offers First Certified TSMC 90-Nanometer USB 2.0 OTG PHY IP (Wednesday Dec. 07, 2005)
DesignWare PHYs for Hi-Speed USB 2.0 and Hi-Speed USB OTG Developed with TSMC’s Production-Proven 90-nm Libraries
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CEVA Introduces Fully Integrated Ultra-Low Power Voice over IP (VoIP) Platform for Dual Mode VoIP/Cellular Phone Applications and Residential Gateways (Monday Dec. 05, 2005)
CEVA-VoP™ features industry's lowest cost per channel; Offering includes complete VoIP software and tools suite, critical for developing VoIP products
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WiSpry and Jazz Semiconductor Partner to Create RF-MEMS for Use in Cellular Handsets and Mobile Communications Devices (Friday Dec. 02, 2005)
WiSpry Innovative RF-MEMS Program Leverages Jazz Leading-Edge RF-CMOS Process Knowledge and 200mm Fabrication Facilities to Accelerate Availability of MEMS