Data converters are at the core of every analog interface to systems-on-chips (SoCs).
As SoCs move into more advanced process nodes to benefit from process scaling, the challenge of integrating the analog interfaces becomes more serious due to the perceived bad analog characteristics of these processes, the reduced supply voltage available, and the large area requirements for these blocks.
Synopsys’ 28-nm DesignWare® Data Converter IP enables SoC designers to effectively move their designs into more advanced process nodes, and take advantage of the cost and power benefits that advanced nodes offer. These IP solutions are based on stateof-the-art architectures, including the Parallel Successive Approximation Register (SAR) architecture, which benefit from the characteristics of the advanced process nodes, while improving the overall analog IP performance and scaling down silicon area and power significantly.
Synopsys DesignWare 28-nm High-Speed Data Converter IP targets applications such as cellular and wireless connectivity as well as multimedia and digital TV. It includes 12-bit high-speed analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), 3 GHz low jitter PLLs, and 12-bit general-purpose ADCs and DACs. The IP features very small area and power consumption, making it the solution of choice for designers who need to meet challenging cost and power targets.
Synopsys’ high-quality DesignWare Data Converter IP solutions have been implemented in more than 200 production designs, giving designers confidence that they can successfully integrate high-performance analog IP into their SoCs with less risk and improved time-to-results.
- Complete portfolio for analog interfaces in 28-nm includes high-speed ADCs and DACs, PLL, and general-purpose ADCs and DACs
- Standard CMOS process with no additional process options
- Parallel SAR 12-bit ADC architecture implementations for up to 320 MSPS sampling rates
- Parallel assembly allows for greater architectural flexibility for specific applications
- Very high performance 12-bit 640 MSPS DAC
- Power consumption reduction of up to 3X and area use reduction of up to 6X over previous generations
- Reduced pin count and smaller external bill-of-materials (BOM) requirements
- Behavioral Verilog model
- Abstract LEF and timing LIB files
- CDL netlist for LVS
- GDSII layout database
- Assembly guidelines and full integration support