The DesignWare® ARC nSIM Instruction Set Simulator provides an instruction accurate processor model for the DesignWare ARC processor families. Such processor models take the software development out of your products? critical path by enabling an early start as well as increased efficiency through enhanced visibility and control. The nSIM models provide a complete and accurate hardware/software interface model of the ARC processors that guarantees binary compatibility of product code between the simulation platform and the hardware. The model is configurable and supports all the ARC processor families, ranging from the high-speed ARC HS Family and the deeply embedded ARC EM Family to the general-purpose ARC 600 Family and the ARC 700 Family for high-performance applications, as well as the ARC AS200 audio processors.
The nSIM model comes with a state-of-the-art JIT compilation engine that leverages the capabilities of multi-core simulation hosts by offloading JIT translation threads from the core that is running the simulation reducing the JIT compilation overhead and significantly speeding up simulation performance. Embedded Microprocessor Benchmark Consortium (EEMBC) benchmarks on a simulation host running at 3.47 GHz show an 18X speed increase, on average, when JIT mode is activated and JIT translation is offloaded to a separate core of the simulation host. As a result, an average performance of 475 MIPS is reached across all 34 tests of the test suite. And over 1,400 MIPS is reached for the EEMBC bezier01 test that benefits most of the JIT activation.
- Single model supporting the ARC EM, ARC 600, ARC 700 and ARC AS200 families
- Available in standalone mode - for processor centric algorithm development and performance tuning at highest simulation speed
- OSCI TLM-2.0 SystemC standard interface for integration with OSCI standard peripheral models
- Virtualizer integration layer provide access to advanced debugging and profiling capabilities offered by Virtualizer
- Very high speed JIT mode benefits from multi-core simulation hosts: 475 MIPS simulated performance for the EEMBC test suite on the ARC nSIM model for the ARC EM family High-speed near cycle-accuracy for system profiling and architectural exploration: up to 95% accuracy compared to RTL at over 25 MIPS (ARC EM family only)
- Seamless switching between different simulation modes by simple debugger command-line invocation; Available for 32/64 bit Windows and Linux simulation hosts
- Models for EIA processor extensions and custom instructions can be added as an extension DLL or as a separate SystemC component