DesignWare IP for PCI Express 4.0 in Samsung 14LPP Process
The multi-channel DesignWare PHY IP for PCI Express® (PCIe®) 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today's demands for higher bandwidth. The PHY is small in area and provides a cost-effective, low-power solution that is designed to support the PCIe 4.0, 3.1, 2.1, 1.1 specifications and to meet the needs of applications with high-speed chipe-to-chip, board-to-board and backplance interfaces.
Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standard’s electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.
The PHY IP reduces both product development cycles and the need for costly field support by employing internal test features. The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity.
Synopsys offers a portfolio of silicon-proven IP for PCIe consisting of controllers, PHYs, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems. As the industry standard for PCIe, Synopsys' solution is in volume production and has been successfully implemented in a wide range of applications.
Built-in self-test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker
Automatic Test Equipment (ATE) test vectors for complete, at-speed production testing. Supports 28-nm, 14/16-nm and 10-nm processes
Designed to the PCIe 4.0 (16 GT/s), 3.1 (8.0 GT/s), 2.1 (5.0 GT/s) and 1.1 (2.5 GT/s) specifications as well as the PHY interface for PCIe (PIPE) 4.3 (8-bit, 16-bit and 32-bit) specifications
Supports a wide range of PCIe lane aggregation up to 16-lanes and full bifurcation
Includes robust backchannel initialization and power management including L1 sub-states
Exceeds electrical specifications in areas of margin and receive sensitivity for a robust design