The E-pak SOC core from Precise-ITC is a multi-rate Ethernet aggregator that supports tributaries at 10GE, 25GE, 40GE, 50GE, 100GE and 200GE in combinations up to 200GE for the E-pak200 or 400GE for the E-pak400.
The E-pak cores provide FlexE 2.1/2.0/1.1/1.0 functionality and implement multi-rate Ethernet PCS and MAC. This versatile device allows users to add or drop sub-channels (for example 10GE) or merge channels (for example 4x25G = 100GE). These dynamic changes do not affect traffic on existing channels.
The north-bound interface from the multi-channel MAC provides a configurable system interface. The Multi-channel MAC manages the mapping between individual MACs and the assigned I/O or I/O group.
The southbound interface is mapped (at the PMA layer) to the on-chip SERDES. The core is responsible for channel alignment and FEC (where applicable).
- Flexible FlexE 2.1/2.0/1.1/ 1.0 core performs mapping and rate adaptation between different channels to a single interface from the multi-channel MACSupports any ethernet combinations (table 1) to maximum data-rate of the device (200G or 400G)Transparent to the far-endFully compatible with IEEE 802.3 2015 and IEEE 802.3 Draft StandardsSuper low latency with minimized fixed and variable delay for network efficiency.
- Supports 1588v2 time stamps and full error handlingSupports 802.3br interspersing express traffic and 802.1Qbb priority flow control (PFC)Logic and power efficient FEC engine
- Combines Ethernet streams at a variety of rates to a single multi-channel interface at the MAC
- The E-pak200 allows access connections supporting 10GE, 25GE, 40GE, 50GE, 100GE and 200GE in any combination on any port or groups of ports to a maximum total bandwidth of 200Gbps
- The E-pak400 allows access connections supporting 10GE, 25GE, 40GE, 50GE, 100GE, 200GE and 400GE in any combination on any port or groups of ports to a maximum total bandwidth of 400Gbps
- Dynamically change rate on any port without affecting existing traffic
- Off-the-shelf, proven technology implementation in Altera and Xilinx FPGAs and ASIC SOC
- Tested and interoperability-proven against Spirent, EXFO and Viavi test equipment
Block Diagram of the E-pak 400G/200G SoC IP Core