24-bit four channel audio ADC with 95 dB Dynamic Range, compatible with Automotive requirements
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-NS
These I/O PADs are compliant with the eMMC 5.1 HS400 specification for use in TSMC’s 28nm HPM process. The I/O PADs integrate seamlessly with Arasan’s eMMC 5.1 host controller IP. These PADs address the need for applications requiring high speed as well as low leakage power. eMMC 5.1 HS400 implementation requires a hard PHY for aligning clock edges.
Features
- VCORE Pre driver voltage
- Min 0.99V
- Typ 1.1V
- Max 1.21V
- VCCQ Post driver voltage
- Min 1.72/2.7V
- Typ 1.8/3.3V
- Max 1.98/3.6V
- TJ Junction temperature
- Min -20cC
- Typ 25cC
- Max 100oC
- VIMAX Maximum input voltage
- 3.7V
- Supports 5 drive strength types [0, 1, 2, 3, 4]
Benefits
- Silicon proven, fully compliant core
- Premier direct support from Arasan IP core designers
- Easy-to-use industry standard test environment
- Unencrypted source code allows easy implementation
- Reuse Methodology Manual guidelines (RMM) compliant verilog code
Deliverables
- GDSII database
- LVS Netlist
- Physical Abstract Model (LEF)
- Timing Models
- Behavioral Models
- Design Integration Guide
- Technical Documentation
Block Diagram of the eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-NS

View eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-NS full description to...
- see the entire eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-NS datasheet
- get in contact with eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-NS Supplier