The Low Latency Interlaken core is compliant with the Interlaken 1.2 and Interlaken look-aside 1.1 specifications.
The System BusWidth, Core BusWidth, and Lane Count are configurable. The System BusWidth is configurable from 1 Word to 16 Words, the Core BusWidth is configurable from 1 Word to 8 Words, and the LaneCount is configurable from 1 Lane to 32 Lanes. Note, 1 Word is 8 bytes.
The core runs cycle accurate, and is designed to run at 390 MHz in Altera SV-3. Every word delivers 25G of bandwidth, e.g. a solution with a 1 Word core can service 4x6.25G. Note, the Core bandwidth has to be equal to or greater than the SerDes bandwidth. The user transmit and receive interfaces are through asynchronous FIFOs, which completely decouple the user clock domain from the cores clock domain.
- 12x10G core latency (no serdes) 50nS in Altera V-2
- 12x10G core latency (no serdes) 13nS in 28nM ASIC
- 3.125 to 25Gbps SerDes support
- Up to 1000Gbps
- Universal single code base supports ILA , ILK and all speed variations.
- Supports Altera Stratix-V, Arria-V, and ASIC.
- Compiles at 500MHz in Altera SV-3
- Configurable number of lanes from 1 to 32
- Size efficient eg: ILA/K-4x10G, soft MAC+PCS; ~10K ALUTs (SV-3)
- In-band and Out-of-Band flow control
- Core BusWidth, 8 to 64 bytes
- BurstShort, Core BusWidth minus 8 to 1024 bytes
- BurstMax, 64 to 1024 bytes
- Logical channel Count, 2 to 64K
- Flow Control Count, 1 to 256
- System/user BusWidth, 8 to 128 bytes
- Loop back & PRBS support
- Full-packet mode and segment mode
- Programmable calendar
- Built-in error detection and interrupt structures
- Configurable error injection mechanisms for testability
- SerDes support for 16,20,32,40,64,80-bit SerDes
- Lowest latency core on the market.
- Lowest gate count core on the market.
- Large timing margin: cores will often run in the slowest speed grade saving money, and compile with push button ease in minutes.
- Single code base for all versions, which drastically reduces internal support and learning curve.
- Customizable synthesis for any speed/target technology. FPGA or ASIC, 65nM or 14nM ASIC node, the RTL can be configured to add or drop pipeline stages to yield the best performing core for the target technology.
- Deliver one code base, as machine readable source (RTL)
- Test bench, synthesis scripts.
- Can generate any version required and use internally for any what if scenarios. Only pay for the version that will be used in the project.
- Datasheet, Userguide, Product Brief, SDC files
Block Diagram of the Low Latency & size Interlaken core for ASIC or FPGA, up to 1,000Gbps, 32 lanes, 56G/lane