The MIPI C+D Combo PHY SERDES comply with mipi.org standard for up to 2.5 Gbps data rate and Single/Multi lane configurations.
- TSMC 40LP- GDS Ready
- Wire-bond & flip-chip packages are supported
Controller is provided by our partners.
DSC (Display Streaming Compression) is supported with our partner Controller.
Easy to integrate at SOC level with flexible form factors
Can be migrated to any CMOS process up to 130nm- call us for a free feasibility study.
- Supports upto 2.5Gbps data rate.
- Standard Interface with SOC –
- PPI compatible interface with higher protocol layer
- APB Interface for IP functional mode configuration
- IEEE1500 8pin interface for DFT configuration
- SERDES features -
- HS & LP receivers & LP transmitter integrated
- Support extension to multiple lanes
- Embedded Low Jitter PLL
- DFT & Test –
- Stuck-at & TFT scan for digital
- Boundary scan (Extest) for integration with SOC scan compressor
- Automated functional test – AC JTAG, Loop-back, RX sensitivity BIST, PLL BIST
- Tests can be done on low cost digital tester
- Low active and stand-by power.
- All power-saving modes implemented for aggressive power saving.
- Lowest area available in the market.
- Flexible number of Tx & Rx Lanes per your application needs
- Lowest Power and Area in the industry
- Customization Services for specific applications, protocols and processes.
- Specification and integration document.
- Physical models : LEF, GDSII
- Spice models for LVS.
- CLP models for low power aware designs.
- Timing models (.libs)
- Simulation models (behavioral and board simulation)
- DFT models and test vectors
- Reference Board with FPGA
- Characterization and compliance reports.
- MIPI.ORG DPHY is used for Mobile Devices on-board connectivity.
- Chip To Chip and Chip to Auxiliaries, e.g. Application processor to
- Camera (CSI)
- Display (DSI)
- Mass Storage (UFS)
- Car Entertainment
- IOT Sensor and device connectivity at low power applications.
Block Diagram of the MIPI C+D Combo PHY upto 2.5 Gbps TSMC 40 LP