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MIPI C-PHY/D-PHY IP in TSMC N7
Synopsys’ integrated DesignWare C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for mobile, automotive, artificial intelligence (AI), and IoT applications. The PHY, for FinFET processes and compliant with the MIPI C-PHY and D-PHY specifications, operates at 4.5Gb/s per lane and 3.5Gs/s per trio respectively for a maximum speed of 24Gb/s. DesignWare C-PHY/DPHY addresses energy requirements by supporting low-power state modes and delivering below 1.3pJ/bit at maximum speed. The PHY offers built-in test capabilities, including pattern generator, logic analyzer, and loopback modes covering all circuits. The DesignWare C-PHY/D-PHY IP interoperates with Synopsys’ ASIL B Ready ISO 26262 certified CSI-2 and DSI/DSI-2 controllers which support key features of the latest MIPI display and camera specifications.
Features
- Compliant with the latest MIPI C-PHY and D-PHY specifications
- Fully verified IP available in TX, RX, or master and slave configuration, including all analog and digital circuitry
- D-PHY mode includes a clock lane and two or four data lanes, each supporting a maximum of 4.5Gb/s per lane in highspeed modes
- C-PHY mode includes two or three trios, each supporting a maximum of 3.5Gs/s per trio in high-speed modes
- Multiple low-power modes, including shut-down, provides multiple test modes for increased reliability
- Ease of integration with the protocol controller layer by implementing the MIPI recommended PPI
- Reliable, high-speed interface for camera and display applications, reducing line count and minimizing cable wires and EMI shielding requirements
Benefits
- Compliant with the MIPI D-PHY specification, v2.1
- 4 Lanes in D-PHY mode up to 4.5 Gb/s per lane
- Compliant with the MIPI C-PHY specification, v1.2
- 3 trios in C-PHY mode up to 3.5 Gs/s per trio
- Aggregate throughput up to 24Gb/s in C-PHY mode and 18Gb/s in D-PHY mode
- Wide PHY Protocol Interface (PPI)
- Low-power escape modes and ultra low-power state modes
- Shutdown mode
- High speed BIST and at-speed scan test
- Master, slave, TX- and RX-only configurations
- Flexible input clock reference and lane/trio swap
- Silicon-proven, robust design available in advanced process technologies
Deliverables
- Databook
- Behavioral model
- LEF file
- LIB file
- GDSII Layout Database
Applications
- CSI-2 Host
- DSI/DSI-2 Host
- CSI-2 Device
- DSI/DSI-2 Device
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