PPA-optimized flexible AI processor IP
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Block Diagram of the PPA-optimized flexible AI processor IP IP Core
AI IP
- NPU IP family for generative and classic AI with highest power efficiency, scalable and future proof
- Ultra low power AI inference accelerator
- RISC-V-based AI IP development for enhanced training and inference
- Tessent AI IC debug and optimization
- RT-630 Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140
- RT-630-FPGA Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140