The Smart Card Interface (SMCARD) provides a communication interface to a Smart Card, meeting all of the requirements defined in the ISO 7816-3 T=0 protocol and supporting the T=1 protocol through software.
The Smart Card Interface uses a single 16-byte FIFO for both transmit and receive. Data transfer to and from the host system is triggered through programmable FIFO thresholds and can be interrupt-driven or executed through DMA for reduced CPU utilization.
The host interface complies with the AMBA 2 APB protocol. Host-accessible control registers provide CPU control of FIFO threshold levels, Smart Card protocol, clock generation, timeout periods, device activation, and enabling/disabling interrupts and DMA. Status registers provide FIFO, interrupt, and error status. An internal state machine switches the Smart Card Interface between various modes in response to hardware and software events.
The connection to the off-chip Smart Card is through chip I/O pads and includes a bidirectional serial data signal (SCDIO), a card detect input signal (SCDETECT), a Smart Card clock output (SCCLK), output signals for Vcc control (SCVCC_EN and SCVCC_n3V5V), and Smart Card reset output (SCRESET).
To reduce chip-level pin count, the Smart Card Interface signals can be shared with other on-chip functions through a General Purpose I/O (GPIO) Controller.
- Compatible with the ISO 7816-3:1997(E) standard
- Support for asynchronous Smart Cards with asynchronous reset
- Support for asynchronous protocol T=0 in hardware and T=1 in software
- Single 16-byte FIFO used for transmit and receive
- Software-configurable interrupts
- Automatic character repetition for protocol T=0
- Automatic convention detection
- Programmable module clock prescaler
- Programmable card clock and baud rate generator
- Programmable card clock and data line buffer (Sustained Tri-state or Push-Pull)
- Programmable debounce counters for card insertion and removal detection
- Clock STOP HIGH and clock STOP LOW for Smart Card power-down mode
- Automatic execution of activation and (emergency) deactivation sequences
- DMA support for transmit and receive
- Debug support: Freeze/suspend Smart Card Interface activity
- Verilog source code
- Integration testbench and tests
- Scripts for simulation and synthesis with support for common EDA tools
Block Diagram of the Smart Card APB Interface (70041) IP Core