The M2WIS adds two-wire slave capability to M8051W and M8051EW designs. Use of standard synchronous design methodology makes this core simple to integrate into both ASIC and FPGA SoC designs.
- Implementation of a two-wire slave interface, compatible with I2C bus standard
- Compatible with I2C Fast and Fast Mode plus signalling
- Supports seven and ten-bit addressing modes, with optional response to general call address
- Can implement flow control with stretching
- Supports any two-wire clock rate, independent of microcontroller clock rate
- Integral data FIFOs minimize processor overhead required to service the link
- Supports both interrupt-driven and polled transfers
- Optional clock prescaler minimises power consumption whilst active
- Power saving mode when the interface is not enabled
- Slave select wake up feature can be used to cold start a M8051W and M8051EW microcontroller, in addition to interrupt driven wake ups
- Binds tightly to M8051W and M8051EW external interrupt and SFR buses with no glue logic required
- The M2WIS is compatible with the I2C Fast protocol. It includes hardware support for seven-bit and ten-bit device addressing modes and a general call address and address ranges. Clock stretching can be achieved under register control in order to implement flow control.
- The core includes the following configurable peripherals as standard: Three timer/counters; Legacy UART; Watchdog timer; Two-wire master interface; Four-wire master interface; Pulse width modulator array, with ramping option.
- All non-legacy peripherals include a configurable clock prescaler, and configurable base addresses and interrupt channels.
- The M8051EW offers three power saving states. These are implemented by dividing the core logic into several synchronous clock domains using optional clock gates. These reduce power consumption by 75% in the idle state and to leakage levels in the stasis and powerdown states.
- VHDL '93 and Verilog 2001 RTL source code
- VHDL and Verilog functional demonstration testbench
- Demonstration assembler code
- Simulation scripts for Modelsim and Cadence
- Synopsys synthesis compile scripts and SDC timing constraint files
- Example Mentor DFT and ATPG scripts
- Example netlist implementation with SDF files
- Detailed product specification and a user guide containing implementation notes
Block Diagram of the Syntill8's Two-Wire slave IP for use with the Mentor M8051W and M8051EW