Search IP on UMC

Maestro Adaptive Workload Manager [PLL] actively adapts to workload changes to boost silicon performance

• Fully SCAN enabled
• Fully customizable to each application
• Wide operating voltages available for DVFS

Maestro Clock Generation Module [PLL], 10x smaller than existing solutions

MIPI C-PHY Combo PHY & Controller (support combo TTL, LVDS, HiSPI)

MIPI D-PHY/C-PHY Combo PHY & Controller (support combo TTL, LVDS, HiSPI)

12-bit 160MS/s Single-Channel ADC

Fractional-N Frequency Synthesizer (40nm - 110nm)

• Fractional/Integer-N frequency synthesizing.
• Spread spectrum clock generation (SSCG) function. (TSMC 40nm (CLN40ULP), UMC 55nm(LP) only)

High-Stable Oscillator - TSMC 40nm(CLN40ULP) / UMC 55nm(LP)

• High accuracy +/-2%, +/-3%, +/-5% at Tj = -40C to +125C.
• The frequency can be adjusted from 150MHz to 160MHz.
• Reference clock is not required.

Integer PLL (40nm - 110nm)

• Has general Integer PLL functions.
• The power supply uses only core voltage.
• Spread Spectrum Tracking.

256x1 Bits OTP (One-Time Programmable) IP, UMC 110 nm 1.2V/3.3V L110AE Process

USB 4.0 Gen3X2 and DP1.4 X4 PHY IP with Type-C connector support

• Worldwide smallest USB4.0 PHY IP in 7nm process.
• Fully compliant with Universal Serial Bus USB4.0 Gen3/Gen2/Gen1, USB3.2 Gen2/Gen1 and 2.0 electrical specifications.

16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+

• Support PCIe G1 to G4 with PCS soft-macro supporting PIPE 4.4.1
• Support xPON applications: Sym/Asym GPON, Sym/Asym 10GPON, Sym EPON, Sym/Asym 10GEPON

Analog I/O + ESD protection for Die-2-die interfaces

• Analog I/Os
• ESD Power protection
• Ground pads