10G TBI Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY layer interfaces of designs with a 10G Ethernet interface 8b/10b PCS. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment. XGMII TBI verification IP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethenet product.
- Follows 10G specification as defined in IEEE 802.3
- Supports all types of 8b/10b PCS TX and RX errors insertion/detection.
- Oversize, undersize, inrange, out of range Packet size errors
- Missing SPD/EPD/SFD framing errors
- SPD/SFD on wrong lane
- CRC Error
- Lane skew insertion
- Disparity error injection
- Invalid /D/ and /K/ character injection
- Variable preamble and IPG insertion
- Comes with 8b/10b PCS Tx BFM, 8b/10b PCS Rx BFM, and 8b/10b PCS Monitor
- Monitor supports detection of all protocol violations.
- Supports Pause frame generation and detection.
- Built in coverage analysis.
- Faster testbench development and more complete verification of 10G 8b/10b designs.
- Easy to use command interface simplifies testbench control and configuration of 10G 8b/10b TX and RX.
- Simplifies results analysis.
- Runs in every major simulation environment.
- Complete regression suite (UNH) containing all the testcases.
- Examples showing how to connect various components, and usage of TXRX BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
Block Diagram of the 10G TBI Ethernet Verification IP Verification IP