IEEE 1149.7 CJTAG Verification IP provides an smart way to verify the IEEE 1149.7 CJTAG component of a SOC or a ASIC. The SmartDV's IEEE 1149.7 CJTAG Verification IP is fully compliant with standard IEEE 1149.7 CJTAG Standard and provides the following features.
- Fully compatible with IEEE 1149.7 standard.
- Can be used as TAP controller (slave) or TAP instruction/data generator (Master) for CJTAG.
- Comes with CJTAG monitor to check and report any protocol violation.
- Supports TAP.7 capability classes T0 to T5
- Supports Extended Protocol Unit (EPU) for classes 0 to 3
- Supports all mandatory and optional EPU commands
- Supports Advanced Protocol Unit (APU) for classes 4 and 5
- Supports 4 and 2 pin interface as specified in IEEE 1149.7 CJTAG
- Supports all mandatory and optional scan formats (JScan, MScan, OScan, and SScan)
- IEEE 1149.7 CJTAG supports following scan terminology
- -> Data Register Scan
- -> Instruction Register Scan
- -> Control Register Scan
- -> Zero-Bit Scan
- Can be extended with user defines instructions and registers.
- Supports optional reset signal.
- On-the-fly protocol and data checking.
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
- Built in functional coverage analysis.
- Callbacks support for BFM and Monitor.
- Status counters for various events on bus.
- CJTAG Verification IP comes with complete test suite to test every feature of IEEE 1149.7 CJTAG specification.
- Faster testbench development and more complete verification of IEEE 1149.7 CJTAG designs.
- Easy to use command interface simplifies testbench control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
- Complete regression suite containing all the IEEE 1149.7 CJTAG testcases.
- Examples showing how to connect various components and usage of BFM and Monitor.
- Detailed documentation of all classes, tasks and functions used in verification env.
- Documentation also contains User's Guide and Release notes.