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MIPI RFFE UVM Verification IP
The MIPI RFFE VIP (RF Front End) is a highly flexible and configurable verification IP that can be easily integrated into any SOC verification environment. Supporting UVM, this RFFE VIP is part of the asureVIP portfolio of implementation-proven VIP offerings.
The MIPI RFFE VIP supports both Master and Slave functionalities and has been entirely programmed in System Verilog and provides support for OVM/UVM based testbenches. The VIP comes with a protocol Bus Monitor which checks for non-compliance with MIPI RFFE specification. The monitor will collect the information from the bus and will frame the high level abstraction classes such as command and address/data frames. During the ‘master passive’ and ‘slave active’ mode configuration the monitor will collect the information from the bus and inform the slave on what command is initiated from the master and how many bytes are to be transferred from slave to Master.
Customers using the asureVIP products do so with the confidence of knowing that they have been independently developed by TVS and successfully deployed by leading SoC companies around the world.
TVS can also offer asureVIP customers an independent hardware verification service (asureVERIF) that not only reduces development costs and time-to-to-market, but also improves product quality.
The MIPI RFFE VIP supports both Master and Slave functionalities and has been entirely programmed in System Verilog and provides support for OVM/UVM based testbenches. The VIP comes with a protocol Bus Monitor which checks for non-compliance with MIPI RFFE specification. The monitor will collect the information from the bus and will frame the high level abstraction classes such as command and address/data frames. During the ‘master passive’ and ‘slave active’ mode configuration the monitor will collect the information from the bus and inform the slave on what command is initiated from the master and how many bytes are to be transferred from slave to Master.
Customers using the asureVIP products do so with the confidence of knowing that they have been independently developed by TVS and successfully deployed by leading SoC companies around the world.
TVS can also offer asureVIP customers an independent hardware verification service (asureVERIF) that not only reduces development costs and time-to-to-market, but also improves product quality.
Features
- Overview
- VIP: MIPI RFFE
- Compliance: MIPI RFFE 1.1 (Extendable to 2.0)
- Language: System Verilog
- Methodology: OVM / UVM 1.1
- Simulators: Cadence Incisive, Mentor Questa, Aldec Riviera-PRO
- Technical Specifications
- Master and Slave Functionality
- Configuration support Master, Slave or both
- Supports Multiple Slaves
- Supports FULL_SPEED and HALF_SPEED
- Supports following frames:
- Command Frame
- Address/Data Frame
- No Response Frame
- Supported Read / Write Commands:
- Register 0 write
- Register Write and Read
- Extended Register write for single slave
- Extended Register Read
- Extended Register write long
- Extended Register Read long
- Multiple slave address value configuration
- Supports Master and Slave Error Injection schemes such as:
- Undefined command Frame
- Command frame with parity error
- Incompatible command length
- Address frame with parity error
Deliverables
- MIPI RFFE VIP
- RFEE Monitor
- Test Suite
- VIP User Guide
Block Diagram of the MIPI RFFE UVM Verification IP Verification IP
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