Questa VIP Family for Display

Questa Verification IP Family for Display supports DisplayPort, HDMI, V-by-One and CEC. QVIP provides a complete verification solution for designs containing display interfaces. Built upon native System Verilog and UVM, QVIP Family for Display provides bus functional models (BFM) with complete functionality on the latest specification for all use models. QVIP Family for Display comes with support for all kinds of stimulus over the interface, ensuring extensive coverage of verification scenarios and exhaustive checking with built-in assertion checks. Architected for ease-of-use, QVIP is easy to integrate in all test benches in minimal time, quickly enabling productive verification. QVIP is integrated with all Siemens EDA functional verification tools and enables verification on all platforms ensuring fast and complete verification closure. QVIP supports on all major simulators (Questa Sim, VCS, and Incisive) and methodologies (UVM). The QVIP Family for Display enables verification of following the interfaces in various use models:
o DisplayPort: AUX, MST, SST, eDP, and HDCP interfaces
o HDMI: FRL, TMDS, HDCP and DDC interfaces
o VByone interface
o CEC interface

• see the entire Questa VIP Family for Display datasheet
• get in contact with Questa VIP Family for Display Supplier