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SD 4.1 / UHS-II Hardware Validation Platform (HVP)
The SD memory card interface dominates the mobile storage markets such as tablets, smartphones, video camcorders, and many other portable or stationary consumer electronics. Designed to be cost effective and Linux based, this SD 4.0 hardware validation platform (HVP) consists of Arasan’s SD4.0 IP mapped into FPGA’s, offering full speed physical connectivity to a complementary SoC host or memory card device. Owing to its active participation in the SDA standards body, and being the first to market SD controller IP, Arasan’s SD controller IP implementation is considered a reference implementation in the industry.
An equally important part of the SD 4 HVP is the software stack, which abstracts all the low level software drivers and hardware to a loadable shared object with easy to use API’s. Hence, an applications software, validation or systems engineer does not need to delve into the protocol and signaling details, and considers the Arasan platform as a programmable complementary device. The SD 4.0 HVP can be used by system developers, system integrator, software developers and system quality analysts to debug as well as validate their products during the product life-cycle.
An equally important part of the SD 4 HVP is the software stack, which abstracts all the low level software drivers and hardware to a loadable shared object with easy to use API’s. Hence, an applications software, validation or systems engineer does not need to delve into the protocol and signaling details, and considers the Arasan platform as a programmable complementary device. The SD 4.0 HVP can be used by system developers, system integrator, software developers and system quality analysts to debug as well as validate their products during the product life-cycle.
Features
- Compliance
- • Supports SD host controller standard spec v 3.0/4.0
- • Supports SD Physical Spec v 3.0/4.0 & UHS-II addendum
- • Supports SDIO Card Spec v 3.0/4.0
- • Supports Embedded SD Physical Spec v 2.1
- SDIO/SD/SDHC/SDXC/UHS-I/UHS-II/eSD Device Validation
- • Sub-LVDS differential signaling compliant with UHS-II specification
- • Supports serial transmission in Full-duplex mode from 390 to 780 Mbps each lane, and Half-duplex mode up to 1.5 Gbps
- • Using 8b/10b encoding for data transmission
- • Low frequency differential RCLK at 1/15th or 1/30th of data rate
- • Multiple power saving modes: Dormant, Line Standby
- • Drives RCLK (52Mhz) for SD Device to generate its clock
- • Supports Data Retries, Boot Code Loading, Bus Master with Scatter Gather DMA
- • CRC16 integrity check for Data and Command
- • Card detection (Insertion / Removal)
- • Host clock rate variable between 0 and 208 MHz
- • Supports SD 1/4-bit and SDIO 1/4-bit modes
- • Direct and extended read/write (IO52, IO53) transactions
Deliverables
- SD/SDIO/eMMC Validation Platform including:
- ◦ SD 4.0/SDIO 4.0/eMMC 5.0 Controller IP implemented in FPGA
- ◦ SD Software Stack
- Linux Installer Package with Documentation
- Documentation
Block Diagram of the SD 4.1 / UHS-II Hardware Validation Platform (HVP)
View SD 4.1 / UHS-II Hardware Validation Platform (HVP) full description to...
- see the entire SD 4.1 / UHS-II Hardware Validation Platform (HVP) datasheet
- get in contact with SD 4.1 / UHS-II Hardware Validation Platform (HVP) Supplier