Search IP on Xilinx

Configurable CAN Bus Controller with Flexible Data-Rate

• Designed in accordance with ISO 11898‐1:2015 specification
• Supports CAN and CAN FD frames
• Supports up to 64 bytes of data frame

ITU 25G PON LDPC Encoder and Decoder

• Support for code rates 38/45 and 57/67
• Uncoded block size of 14592 bits

Time aligned Frequency Generator core

• Configurable frequency signal generation (0-10MHz) in 1Hz steps
• Configurable polarity
• Output delay compensation

SDA OCT V3.0 Encoder and Decoder

• Low-power and low-complexity design
• AXI4-Stream data and configuration interfaces for a seamless integration
• Collection of statistical information

CCSDS 131.2 Wideband Demodulator

• Compliant with CCSDS 131.2-B-1
• Supports ACM mode
• Supports roll-off factors 5%, 10%, 15%, 20%, 25% and 35%

DDR5 Registering Clock Driver (RCD) (DDR5RCD01)

• Compliance as per JEDEC's JESD82-511
• In I3C mode, SCL Operating speed 12.5MHz as Maximum
• DDR5 server speeds up to 4800MT/s

32-bit High Performance RV32GC Single/Multicore RISC System-on-Chip

• High Performance 32-bit RV32GC CPU
• Proprietary 6-stage pipeline
• Single or multicore implementation

32-bit High Performance RV32GC Single/Multicore RISC Processor

Power Management IC - I3C Basic Interface IP

• Maximum Operating speed 12.5MHz
• Support In-band Interrupt
• Bus reset is supported

LPDDR5X DDR Memory Controller

• JEDEC LPDDR5X/LPDDR5 devices compatible
• Data rates up to 8533Mbps
• Multiple ARM AMBA AXI4/AHB/APB & Custom interfaces

AXI4 Memory-Mapped to/from AXI4-Stream DMA

• Independent AXI4 compliant single channel modules
• AXI4-Lite port for access to control and status registers

Generic Waveform Generator

• Scalable approach
• Huge set of supported protocols
• Variable set of driver ans stimuli units possible