A Novel Modeling and Verification Environment for Rapid IP Prototyping
Mikhail Baklashov, Manish Bhattarai, Simantix Systems, Inc., Sunnyvale, CA
This paper proposes a new functional level abstraction, called SL, its syntax, and features developed by an extension of Scheme. The SL abstraction has been further implemented in a MetaSL - the testbench development, simulation and modeling environment. A functional language based verification technology is described, as opposed to OOP paradigms, to solve the massive time and cost problems they take to develop software. Then, this paper shares the approach, methodology and the results of the SL implementation of the JPEG2000 Encoder and attempts to compare and contrast this accomplishment with the C++ implementation. Specifically, our goal will be to establish the amount of time required and thus lines of code used to implement various procedures, functions and algorithms in both languages.
Increasing SoC complexity and shortening time- tomarket for modern ESL systems dictate for ultra- high abstraction languages and intelligent tools to be used in very fast algorithm development for new IP's. Traditionally, C, C++, SystemC and other C++ flavors and tools have been used for prototyping algorithmic cores. In developing IPs and verification environments, designers who use lower level languages spend considerable amount of time to solve language related issues such as memory allocation, programming even simple algorithms, compatibility issues when using different compilers, and other language details, whereas all the attention must be focused on functional specification requirements. Simantix's functional language - SL, testbench development and modeling environment - MetaSL, centered around a selected IEEE Scheme standard and a patent- pending technology, were built to model and verify extremely complex systems. The showcase feature of SL is its ability to enable design and verification of large functional systems using abstractions. Simantix's innovation lets designers approach a hardware model from a very high- level of abstraction and yet is still capable of verifying timings at a detailed cycle level. The simplicity of SL is not only limited to hardware designs but software modeling code has also been proven to have been reduced by as much as 50%. In this paper, in Section 2, we first start with an overview of the proposed technology, modeling and verification development environment. We then, in Section 3, will present the core of the technology and demonstrate different SL abstractions. A real- life modeling example will conclude the section. Section 4 will continue with internals of the environment implemented in terms of two tools. The technology application will be shown in Section 5, that will highlight the technology in modeling JPEG2000 encoder. Experimental results will follow in Section 6. Compilation features of MetaSL for FDWT (Forward Discrete Wavelet Transformation) will be reported, such as an increase in performance over its interpreted execution. Section 7 will conclude the paper.
2. Proposed Technology
Simantix's functional verification technology  , derived from Scheme, keeps its elegant syntax and semantics, and extends it with additional abstractions and internal simulation engine. A top block diagram of the Simantix's system- level simulation and verification environment is shown in Fig. 1.
Fig. 1 Verification Environment
The technology has been developed to significantly increase the productivity of verification engineers and reduce risk in modeling and testbench development. Scheme, mostly used in Artificial Intelligence (AI) applications, was designed not by piling feature upon feature, but by removing the weakness and restriction of such a design with a very small number of rules for forming expressions. These set of rules without any restrictions on their composition, form a practical and powerful tool that is efficient and flexible to support most major programming paradigms in use today. The environment comprises the MetaSL simulator, system or functional design specification, the Visual MetaSL composer, functional language (SL), verification functions, and model functions. The simulator verifies the system by functional simulation. The composer provides visual programming features and gives users a source code reuse and guides for better system modeling techniques. The model functions written in SL or another conventional languages model behavior of the system. The verification functions verify that the behavior modeled by the model functions conforms to the functional design specification.
3. Simantix Language - SL
3.1 SL Overview
SL language is built around the selected IEEE Scheme standard. Scheme, a first dialect of Lisp, is a well designed functional language that has been adopted as an alternative to other programming languages. The environment is interactive, allowing for incremental development and testing parts of user programs. Programs written in the language can also be compiled for Intellectual Property (IP) protection and to make programs run fast.
Fig. 2 Function Classification
3.2 Function Classification
In the Simantix's simulation and verification environment functions can be classified into verification functions and model functions connected by concurrent interfaces, as shown on a top level view in Fig. 2. The verification functions further may comprise one or more monitors, checkers, user- defined tests, verification sequences, assertions, or any combination of the above functions. They verify the correctness of the functional blocks in the system using the MetaSL simulator. SL functions include the model functions for modeling the functional blocks in the system to be functionally exercised by the MetaSL simulator. The model functions can also be selectively expressed in a selected RTL HDL or conventional programming languages, such as C or C++. The RTL HDL is selectively Verilog.
3.3 Temporal Abstraction
SL has temporal constructs similar to those in Verilog and other HDL languages, (always @ (posedge clka)...), (@ (negedge clkb)), etc. . It is a very high abstraction level language with all of the powerful functions defined in the standard. The language has additional functions for defining interface signals, connecting the interfaces, and a function to define multiple clocks and their parameters, such as skew, positive phase, negative phase, and initial value. Users can control and observe interface signals concurrently from different threads. When writing testbenches, users may synchronize their tests to different clocks. There are primitive simulation control functions like ($simulate...), ($stop), ($resume) and others similar to HDL simulation environments, which might be used for more advanced user- defined functions. SL language has very high -level, efficient means of abstraction allowing to program very complicated tasks. The interactivity combined with the possibility to compile makes the SL language easy to employ in testbench, simulation, modeling and verification environments.
3.4 Concurrent Interfaces
Fig. 3 shows the concurrent interfaces connecting the verification functions with the model functions and concurrently transferring abstracted signals 1 and 2 between the functions. The abstracted signals 1 carry values of types expressed as generic or aggregate SL types. To control states of the concurrent interfaces SL further comprises control functions that drive the abstracted signals 1 with values of SL types. To observe the states of the concurrent interfaces SL further comprises observation functions that sample the abstracted signals 2 values of SL types.
Fig. 3 Concurrent Interfaces
3.5 SL Syntax
SL supports standard numerical types - complex, real, rational, integer, and numerical operations - multiplication, division, addition, subtraction, quotient, modulo, etc. Conditional expressions, bitwise operations, characters, strings, lists, pairs, arrays, bit-vectors, file operations, recursion and many other features of SL make it a very simple yet a powerful language. What distinguishes SL from other implementations of Scheme is its support for temporal expressions. Temporal abstractions, one of Simantix's innovations, can be used to synchronize SL function executions with time and events during simulation. Some of the important temporal features supported are: single or multiple clock functions, continuous monitoring with the clock and continuous monitoring with an event. Brief examples of these features follow:
(let ((loop (lambda (n)
(@ (posedge clkA))
The above example is a single clock delay of clock clkA and the statements that follow will wait for the positive edge of the specified clock.
(@ (posedge clkA)
<sequence- of- functions> )
This example shows a temporal block of a sequence of functions waiting to be executed whenever a positive edge of the clock clkA occurs. Similarly in continuous event monitoring, the clock is replaced with the signal that needs to be monitored, and the statements that follow it will be executed whenever the signal is triggered. The complete language syntax is described in .
3.6 Modeling Example
In what follows is a real- life example of a verification function to be used to test a microprocessor model. Function verify, shown in Fig. 4, is a function of two arguments that are a sequence of microcode instructions to be executed on the model and the total number of instructions to be simulated. This function is not a user-written but automatically generated in the composer from a conceptual level of abstraction.
|(define (verify seq n) |
(upload- instruction- memory inst- instr-mem 1 seq)
(counter- load inst- pc 1)
(let loop ((i 0))
(@ (posedge clk)
(register- latch inst-mar (counter- read inst- pc)))
(@ (posedge clk)
inst- instr- reg
(memory- read inst- instr-mem (register- read inst-mar))))
(@ (posedge clk)
(instruction- decode (register- read inst- instr- reg) 1))
(@ (posedge clk)
(counter- inc inst- pc))
(if (< i (- n 1))
(loop (+ i 1)))))
Fig. 4 Verification Function
The first action in the verification function is to upload an instruction memory with the sequence and initialize a program counter to the initial address. Two function applications: uploadinstruction- memory and counter- load, perform the action. Each internal function application has its corresponding instance as a first argument. The action, when executed, modifies instances of the instruction memory and program counter. The next action is an iteration that is performed for every instruction in the sequence. Highly being dependent on the microprocessor model, the action is executed in four cycles. SL temporal abstractions are employed for modeling the action. In the first clock cycle a memory address register is latched with the program counter value. During the second clock cycle a chain of three function applications is modeled. First, as a result of function application register- read, an address value from the memory address register becomes available for function memory- read. Second, an instance of the instruction memory modifies its state to point to the first instruction in the sequence. The evaluated result of function memory- read is the first instruction value that, in turn, becomes available for function register- latch. Last, an instance of instruction register changes its state with the first instruction value. An instruction decoding happens during the next clock cycle. In the last clock cycle the program counter is being incremented to trigger the next instruction handling.
4. Verification Environment
The verification environment shown in Fig. 5 provides components to support the intelligent modeling and testbench development. It has an embedded built- in simulator that simulates behavioral models by using stimuli generated by test programs and controlled by a multiple clock engine. An analyzer component analyzes the behavioral model and testbench programs to extract information needed for an event scheduler component. The analyzer provides shell and control interaction between user- defined functions and the MetaSL environment. The event scheduler component is an internal environment block that receives control and data temporal dependencies from the interpreter, transforms and supplies the dependency information to the simulator. The multiple clock engine component generates multiple clocks for the simulator based on user -defined clock definitions. In addition, the MetaSL environment has links to commercially available RTL simulators and allows for designers to create efficient and complete functional verification environments, noticeably reducing programming effort and development time. In generating testbenches and developing models, designers employ MetaSL in an interactive mode that accelerates programming and debugging because it is not necessary to recompile their source code each time a change in the code is needed. In addition, SL functions can be reloaded on the fly and even into running applications - features which are extremely convenient during initial stages of code development, and non- existent in compiled type languages. The code is compiled if and when no additional changes in testbenches or models are needed. The performance of the target compiled code in all cases is near the C language performance and faster than C++. Another distinctive feature of SL and Simantix's technology is that both allow for easy abstraction implementations. By using high- order functions and functional language features, designers can easily abstract very complicated algorithmic and system behaviors, and make further manipulations with abstractions, such as executing, transferring through interfaces, storing, comparing, and many others.
Fig. 5 Verification Environment
4.2 Visual MetaSL
The Visual MetaSL integrated testbench development environment  includes the MetaSL as its internal simulation engine. The graphical environment facilitates the usage of the MetaSL and provides features that help users benefit from the characteristics of SL language even if they are not previously familiar with it. The composer module enables to capture functional design specifications, build interfaces and behavioral models, generate verification actions. It helps in correct programming SL generic and temporal functions, instantiating user- defined functions and intelligent selecting few hundreds of SL functions. One of the features visual programming, gives users a source code reuse and guides for better system modeling techniques, while the flexibility of developing testbenches are preserved. Experienced users will also find several advantages when using the technologies Visual MetaSL offers. For extremely complex systems Visual MetaSL essentially simplifies the modeling process and creating verification tests. For example, for microprocessor systems, the composer can be adjusted to verification at instruction cycle levels and to provide generic functions used in most microprocessor designs, such as instruction and data memories, register file, program counter, accumulator, alu, etc. Users can easily generate instructions by instantiating these functions whenever needed and calling them at different clock cycles for every instruction. The environment will prompt users with relevant selections and instantiate functions automatically. Users may instantiate generic testbench functions such as random and constrained instruction sequence generators, instruction uploading and other modules, and schedule execution of functional checkers. Visual MetaSL debugging feature helps display the content of registers and memories, function execution traces and graphically monitor abstract signals on concurrent interfaces. The environment also provides full automation of compiling SL libraries, generating and managing SL projects.
5. Modeling JPEG2000 Encoder
5.1 JPEG2000 Overview
JPEG2000 is a new international standard technique for image compression proposed by the ISO/IEC international organizations, and its prototyping in C++ has been recently published . JPEG2000 supports lossy and lossless compression of single or multiple component imagery . JPEG2000 encoder consists of many different algorithmic intensive operations that require fast prototyping. A lower level design of JPEG2000 would require a lot of time and effort in contrast to an SL implementation while managing complexity by means of high- order functions. Compilation of some JPEG2000 functions in SL also remarkably improved performance in the encoder development. The fast algorithmic prototyping and compilation feature of SL helps engineers design in a simple yet powerful syntax and semantics.
5.2 General Encoder Structure
The SL implementation of the JPEG2000 Encoder has been accomplished at Simantix. It was started with a goal to create functional design and verification IP which could be used as a reference model for its RTL core. The main idea behind the JPEG2000 encoder is to get a compressed JPEG2000 output image file from a raw image data. The preprocessing block of the JPEG2000 encoder takes the input image file, parses through the data and stores the different image components in separate arrays after DC-level shifting, ensures that the image samples are in the nominal dynamic range. RCT, an inter- component transform, is performed on the image samples to reduce the correlation between components, greatly improving coding efficiency. Intra- component transform, FDWT is performed separately on the image components to split it into numerous frequency subbands. This ensures that the data can be more efficiently coded than untransformed data due to the statistical properties of the subbands. The transformed data is then coded using bit- plane encoding process which generates a sequence of symbols which are fed into an arithmetic MQ coder. Coded bytes generated from the MQ coder are packaged into packets after a particular organization on the coded data in the output code stream. Packets include the header -indicates the kind of data in the packet, and the body - the actual coded data itself. This collection of packets organized in a desired fashion with original image information and various coding attributes indicated in specific file header creates a compressed JPEG2000 image file.
6. Experimental Results
The development of JPEG2000 encoder blocks and the verification IP in SL was a formidable task, but the high order function, defining functions inside functions, mutable data structures, and automatic memory management features accelerated the design process. The MQ coder implemented using C++ for a reference JPEG2000 design project was compared to an SL implemented MQ coder in terms of performance, design complexity and time taken. The performances of both designs were very similar in terms of speed, but the SL implementation was 300 lines of code compared to 500 lines for the C++. Being minimal in syntax and having only a few ways of forming compound expressions made SL simpler than C++ without having to worry about language details and memory management. This resulted in transparency with language details and development time was dedicated on the design issues. Thus reduced programming effort and development time was evident for the SL implementation, making it a more desirable functional modeling and verification language. Table 1 shows additional experimental results for four selected functional modules of the encoder and compares the number of lines in their both implementations, SL and C++. The time taken to code the modules, MQ-Coder, RCT, FDWT, in SL ranged from 5 to 10 3-student weeks depending on their previous software engineering experiences, and that included learning SL, MetaSL and the JPEG2000 standard as well. Rapid development time while ensuring comparable performance to a low level implementation of any algorithmic intensive functional block is another reason designers look at SL for functional prototyping. The algorithmic intensive RCT and FDWT functional blocks of the SL implementation of JPEG2000 were compiled into internal SL functions.
|Functional Module || SL ||C++ |
| #lines ||#lines |
|MQ-Coder || 278 ||671 |
|RCT ||132 ||163 |
|FDWT ||257 ||624 |
|BitplaneEnc. ||1246 ||1794 |
Table 1. Experimental Results
The compilation of RCT resulted in up to 50x improvement in some cases over the interpreted execution. The more algorithmic complex FDWT function yielded 100x performance boost when compiled. Thus the compilation feature of SL can be easily exploited to gain significant performance boost to make it comparable to a very fast low level implementation which normally takes significant amount of time and effort to accomplish.
Functional verification of any design - hardware or software, takes significant time block of a design cycle. Design engineers are constantly looking for innovative methods to cut back on the time- tomarket of new systems. Simantix's functional language SL, and development and modeling environment MetaSL, were built to model and verify complex systems with ease. Simantix technology, based on the selected IEEE Scheme standard, ensures high levels of abstraction and modeling, offering significant advantages for large scale system design and functional verification. SL alleviates design engineers capturing common patterns of usage in specifications and creating powerful abstractions. SL implementation of JPEG2000 cemented the fact that with less programming effort and development time than C++ model similar results in performance are achieved. Compilation features of Simantix technology can also be employed to gain significant performance gain over interpreted execution while using high- level abstraction.
 M. Baklashov, L.-T. Wang, Method and Apparatus for Functional Language Temporal Extensions, Dynamic Modeling, Simulation and Environment, US Patent Application, 11/029,345, January 6, 2005.
 Simantix, MetaSL User Guide. Available at www.simantix.com.
 Simantix, SL Language Reference Manual. Available at www.simantix.com.
 Simantix, Visual MetaSL User Manual. Available at www.simantix.com.
 JPEG2000: Image Compression Fundamentals, Standards and Practice, David S. Taubman, Michael W. Marcellin, 2004.
 JPEG2000, Part 1, Standard (ISO 15444).