English
True design-for-manufacturability critical to 65-nm design success
Dwayne Burek, Magma Design Automation
(11/07/2007 5:29 PM EST) -- EE Times
True design for manufacturability (DFM) at 65-nm and below technology nodes has become more critical due to the shrinking of the critical dimensions of structures on the chip where the same absolute physical variations can result in relatively large electrical variations.
At 65 nm and below, lithographic effects become the biggest contributor to manufacturing variability. The problem is that the features (structures) on the silicon chip are now smaller than the wavelength of the light used to create them. If a feature were replicated as-is in the photomask based on the lithographic image, the corresponding form appearing on the silicon would drift farther and farther from the ideal, with the decreasing feature sizes associated with the newer technology nodes.
The way this is currently addressed in conventional design flows is to postprocess the GDSII file with a variety of reticle enhancements techniques (RETs), such as optical proximity correction and phase-shift mask. For example, the physical design tool modifies the GDSII file by augmenting existing features or adding new features, known as subresolution assist features, to obtain better printability. This means that if the tool projects that the printing process will be distorted in a certain way, it can add its own distortion in the opposite direction, attempting to make the two distortions cancel each other out.
The issue is that every structure in the design is affected by other structures in close proximity. That is, if two geometric shapes are created in the GDSII file and photomask in isolation, these shapes print in a certain way. But if the same shapes are now located in close proximity to each other, interference effects between these shapes modify each of the shapes, often in nonintuitive ways. The results of all these effects are variations in timing, noise, power consumption and, ultimately, yield.
Manufacturing and yield problems typically fall into four main categories: catastrophic, parametric, systematic (feature-driven) and statistical (random). Catastrophic problems are those such as a missing via, which cause the chip to fail completely. By comparison, parametric problems leave the chip functioning, but out of its specified range, such as a 500-MHz device that runs at only 300 MHz, or a part that is required to consume less than 5 W of power that actually consumes 8W. The origins of both catastrophic and parametric problems can be subdivided into systematic (feature-driven) effects and statistical (random) occurrences.
(11/07/2007 5:29 PM EST) -- EE Times
True design for manufacturability (DFM) at 65-nm and below technology nodes has become more critical due to the shrinking of the critical dimensions of structures on the chip where the same absolute physical variations can result in relatively large electrical variations.
At 65 nm and below, lithographic effects become the biggest contributor to manufacturing variability. The problem is that the features (structures) on the silicon chip are now smaller than the wavelength of the light used to create them. If a feature were replicated as-is in the photomask based on the lithographic image, the corresponding form appearing on the silicon would drift farther and farther from the ideal, with the decreasing feature sizes associated with the newer technology nodes.
The way this is currently addressed in conventional design flows is to postprocess the GDSII file with a variety of reticle enhancements techniques (RETs), such as optical proximity correction and phase-shift mask. For example, the physical design tool modifies the GDSII file by augmenting existing features or adding new features, known as subresolution assist features, to obtain better printability. This means that if the tool projects that the printing process will be distorted in a certain way, it can add its own distortion in the opposite direction, attempting to make the two distortions cancel each other out.
The issue is that every structure in the design is affected by other structures in close proximity. That is, if two geometric shapes are created in the GDSII file and photomask in isolation, these shapes print in a certain way. But if the same shapes are now located in close proximity to each other, interference effects between these shapes modify each of the shapes, often in nonintuitive ways. The results of all these effects are variations in timing, noise, power consumption and, ultimately, yield.
Manufacturing and yield problems typically fall into four main categories: catastrophic, parametric, systematic (feature-driven) and statistical (random). Catastrophic problems are those such as a missing via, which cause the chip to fail completely. By comparison, parametric problems leave the chip functioning, but out of its specified range, such as a 500-MHz device that runs at only 300 MHz, or a part that is required to consume less than 5 W of power that actually consumes 8W. The origins of both catastrophic and parametric problems can be subdivided into systematic (feature-driven) effects and statistical (random) occurrences.
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