Customizable SoC SPEAr from STMicroelectronics Solving Time to Market Issues
By Alain Pasteur, Henry Le-Henaff, Bruno Cristofoli - STMicroelectronics
Some of the most common known issues any equipment manufacturer needs to solve are Time To Market and Time To Volume strong constraints. These issues are also linked with an increased fragmentation of the final products portfolio to be offered, even if often these products are using the same kernel of basic SoC product.
SPEAr concept is one of the most suitable versatile but standard SoC for a customer to solve these issues
A SoC with about 80% of the silicon already debugged and tested and still allowing more then 20% of customization capability provides customer a great tool to focus on the core business. A flexible, easy and quick to use development tools gives the right speed of design and integration and solves the Time To Market issue.
A SoC already pre-qualified offers also a solution for the Time To Volume issue.
The capability to run different customizations at a fraction NRE cost versus an ASIC solution provides the best solution for today market dilemma: several models a year to explore potential niche segments.
STMicroelectronics customizable processor family, called SPEAr® (Structured Processor Enhanced Architecture), supplies a powerful digital engine that offers the possibility of designing special user functions with very low development time and cost.
The family is based on an ARM core architecture that maximizes hardware and software performances; it includes an advanced bus system and IPs for connectivity and memory interfaces. The user functions can be embedded in the configurable logic block.
SPEAr® concept provides high performances SoC and full custom design capabilities with a quick development cycle.
SPEAr® products are full ST quality standards and every customization does not require a further qualification process because the customization technology is already proven.
SPEAr® products are SoC with embedded functional blocks and innovative design model that makes a project customization easy, reliable, quick, and affordable.
Its roadmap takes advantage of the most leading edge technology at 110nm, 90nm, and 65nm HCMOS processes and beyond.
SPEAr® customization capability enables flexible platforms with the ability to embed Customer, 3rd parties portfolio IP or ST IP, and more without changing any of the typical tape-out validation.
By using mask-configurable logic the embedded region allows cost effective derivative devices with fast time-to-market and reduced engineering expense (compared to a quite long and expensive ASIC design model).
The typical ASIC design models allow the designer to put together functional blocks according to a project requirements. SPEAr® enables designers to embed functional blocks (standard or custom IP) within a pre-designed, tested, and validated system architecture featuring leading ARM processors, peripheral/memory controllers and state of the art connectivity.
Adapting the project requirements to SPEAr® architecture is easy, fast, and reliable.
The customizable logic accepts any digital project requirements by interconnecting metal and via layers, combining logic tiles with a very high integration yield.
Moreover the customizable logic allows the design of a single platform device to respond to changes in the customers specification
Fig. 1 - SPEAr® versus ASIC comparison
Fig. 2 - SPEAr® roadmap
Of course SPEAr® family components are different: single/dual cores, customizable logic size, connectivity and so on, but have been designed sharing some important architectural concepts and therefore providing scalable solutions:
State of art ARM cores (from ARM9 to Cortex A9) single/dual cores
Very good memory interface; especially for the DRAM path. Multiport memory controllers, providing buffers for each SoC internal path (main IPs are connected via dedicated bus), are used to solve latency issues and optimize memory access.
Rich set of connectivity IPs (USBs, Ethernet etc.) having dedicated busses for the memory controller ports connection.
HW accelerators and HMIs (JPEG codecs, crypto engines, LCD controllers with touchscreen capabilities etc.)
Internal multilayer bus matrix to avoid bottlenecks and latency issues accessing low speed peripherals
A set of legacy IPs (UARTs, timers, ADC etc.)
The customizable block with SRAM resources. SRAM blocks (single and dual ports) can be configured to act as IPs buffers (FIFOs, local memories et.) or directly accessible by the ARM core like other Master peripherals. Each memory cut has dedicated address/data/control paths connected to the customizable logic so the customization process can freely create the required memory sizes (different depths and widths). Since each memory cut is independent, the total provided bandwidth is really impressive; for example SPEAr600 provides 28 singleport and 12 dualports SRAM cuts (32bits data wide), so running them at 166MHz it can achieve 276 Gbits per second (34.5GBytes per second: [28 + 2 x 12] x 4 x 166MHz).
Fig. 3 - SPEAr® typical architecture
SPEAr® emulation and simulation
SPEAr® offers two options to verify the whole platform behavior:
Simulation of the netlist of the whole SoC (customer IPs embedded + SPEAr®)
Emulation of the customizable logic with an external FPGA connected to SPEAr®.
The customer can plan the most appropriate verification methodology using either the simulation or the emulation one.
Both methodologies may be used without changing the design
Fig. 4 - SPEAr® development board
Examples of SPEAr® benefits
The following examples show the customization capabilities of these SoCs and are referring to SPEArBasic, the cheaper device providing 300Kgates (100% utilization ratio).
A. VoIP applications:
SPEAr family solves most of the equipment manufacturer needs.
SPEArBasic-STD, a VoIP version of SPEArBasic, has been a low effort and low cost way for STM to enlarge its VoIP portfolio with a low cost low consumption high end device.
Customization contains the following IPs targeting VoIP:
- TDM with up to 1024 timeslots that can be switched,
- 64 FXS/FXO channels can be connected glue less,
- Up to 16 of those channels can be buffered for VoIP communication (i.e. 30ms packets),
- ARM926EJ S has a computation power of twelve G.711 or three G.729 channels
- LCD controller is 24 bits XGA,
- Keyboard controller is 9*9 keys wide,
- Ethernet 10/100 is in the fixed part.
With this topology, low end IP phone electronic BOM has achieved a very competitive cost.
Fig. 5 - SPEAr® VOIP customization
B. Other applications:
- With embedded crypto accelerator, SPEArBasic-STD can be used for any network application.
- With SDIO controller, SPEArBasic-STD can be used in handsets or photo frame.
- With JPEG codec, SPEArBasic-STD can be used for MJPEG video.
- Finally, with around half of the customizable space free, a newer version of SPEArBasic-STD could embed also a videodecoder or at least an accelerator and be used to build a very low cost Visio phone.
Three months were necessary from specification to new cells completed with top mux designed to match the different use-cases, then two weeks to merge the new cells with standard cells in the customization. Tape out was released beginning 2008, and first samples were on the table end of February 2008.
This product will be the base of a reference design available soon for customers
Second example of SPEAr® approach benefits through SPEAr® Basic Automation
By getting in account several requests coming from different customers, STM took the decision to build a standard part which would fit several different applications in the Automation segment.
Customer request collection and marketing investigation lasted one quarter. The design activity and the end of the diffusion process will happen by end 2008 and the plans to ship the first samples are by early 2009.
In Q109 STM will introduce also an evaluation board based on that silicon.
SPEAr® concept is used as a quick Standard Product generator either in STMicroelectronics or at a final customer.
Even more, a customer having different applications can still think about a single customization, feeding all the available customizable logic space and designing several configuration/pin-out modes tailored for every single application.
Fig. 6 - SPEAr® automation customization